Versal ACAP AI Engine Programming Environment User Guide (UG1076) - 2021.2 English

Document ID: UG1076
Release Date: 2021-12-17
Version: 2021.2 English

Overview
Navigating Content by Design Process
AI Engine Architecture Overview
AI Engine Tile Architecture
Tools
Documentation
Introduction to AI Engine Programming
Prepare the Kernels
Creating a Data Flow Graph (Including Kernels)
Run-Time Ratio
Recommended Project Directory Structure
Compiling and Running the Graph from the Command Line
Window and Streaming Data API
Data Access Mechanisms
Window-based Access
Synchronous Window Access
Asynchronous Window Access
Stream-based Access
Window Operations for Kernels
Window Data Types
Moving the Current Read/Write Position Forward
Moving the Current Read/Write Position Backward
Reading Data from an Input Window
Reading and Advancing an Input Window
Reading and Decrementing an Input Window
Writing Data to an Output Window
Writing and Advancing an Output Window
Stream Operations for Kernels
Stream Data Types
Reading and Advancing an Input Stream
Writing and Advancing an Output Stream
Using Streams in Parallel
Packet Stream Operations
Packet Stream Reading and Writing
Packet Processing
Run-Time Graph Control API
Graph Execution Control
Basic Iterative Graph Execution
Finite Execution of Graph
Infinite Graph Execution
Parallel Graph Execution
Timed Execution
Run-Time Parameter Specification
Specifying Run-Time Data Parameters
Run-Time Parameter Update/Read Mechanisms
Parameter Update/Read Using Graph APIs
Chained Updates Between AI Engine Kernels
Run-Time Graph Reconfiguration Using Control Parameters
Bypass Control Using Run-Time Parameters
Sharing Run-Time Parameters Across Multiple Kernels
Run-Time Parameter Support Summary
Specialized Graph Constructs
Look-up Tables
Static File-scoped Tables
Global Graph-scoped Tables
Shared Graph-scoped Tables
FIFO Depth
Stream Switch FIFO
DMA FIFO
AI Engine Tile DMA Performance
Kernel Bypass
Explicit Packet Switching
Packet Switching Graph Constructs
Packet Switching and the AI Engine Simulator
Location Constraints
Kernel Location Constraints
Buffer Location Constraints
FIFO Location Constraints
Area Location Constraints
Hierarchical Constraints
Buffer Allocation Control
C++ Kernel Class Support
C++ Template Support
Multicast Support
AI Engine/Programmable Logic Integration
Design Flow Using RTL Programmable Logic
Design Considerations for Graphs Interacting with Programmable Logic
PL Interface Tile Capabilities
AI Engine-to-PL Rate Matching
AI Engine-PL Interface Performance
Using a Virtual Platform
Virtual Platform
FileIO Attributes
PLIO Attributes
GMIO Attributes
Programming Model for AI Engine–DDR Memory Connection
Hardware Emulation and Hardware Flows
Performance Comparison Between AI Engine/PL and AI Engine/NoC Interfaces
Enhanced Programming Model
Compiling an AI Engine Graph Application
Setting Up the Vitis Tool Environment
Inputs
Outputs
AI Engine Compiler Options
Mapper and Router Options
Viewing Compilation Results in the Vitis Analyzer
Graph and Array Details
Kernels
Programmable Logic (PL)
Buffers
Ports
Nets
Tiles
AI Engine Compiler Guidance
Simulating an AI Engine Graph Application
x86 Functional Simulator
Compiling the Design
Data Snapshots
Deadlock Detection
Trace Report
Memory Access Violations and Valgrind
Using GDB
Macros
Printf() Macros
Using printf() in Kernels
Limitations
Memory Model
Graph API Calls
Preprocessor Considerations
Simulation Output File Processing Considerations
adf::headers Constraint and aie_api Include Files
Packet Switching and RTP
Packet Switching
Synchronous and Asynchronous RTP
Best Practices
Software Emulation
Reusing x86 Simulator Options
AI Engine SystemC Simulator
Simulator Options
Simulation Input and Output Data Streams
Simulating Global Memory
Hardware Emulation
Reusing AI Engine Simulator Options
Enabling Third-Party Simulators
Performance Analysis of AI Engine Graph Application during Simulation
AI Engine Simulation-Based Performance Analysis
AI Engine Simulation-Based Profiling
AI Engine Simulation-Based Value Change Dump
VCD File Generation
AI Engine Trace from VCD
Viewing the Run Summary in the Vitis Analyzer
Trace View Data Visualization
Window Data Analysis
Supported Window Data Types
Stream Data Analysis
Supported Stream Data Types
Cascade Data Analysis
Data Display Limitations
Cross-Probing
Trace Compare
AI Engine Stall Analysis in Vitis Analyzer
Performance Metrics
Lock Stall Analysis
Stream Stall Analysis
Cascade Stall Analysis
Memory Stall Analysis
Using Trace Compass to Visualize AI Engine Traces
Trace Views
Performance Analysis of AI Engine Graph Application on Hardware
Profiling the AI Engine
Event Profile APIs for Graph Inputs and Outputs
Profiling Platform I/O Port Bandwidth
Profiling Graph Throughput
Profiling Graph Latency
Profiling Port Throughput
Run-Time Event API Performance Counters
Profiling the AI Engine in Hardware
Profiling the AI Engine and Memory Modules
Profiling for AI Engine
Profiling for Memory Modules
Core versus Memory Module Metric Sets
Profiling Flows
XSDB Flow
XRT Flow
Viewing Profiling Results using Vitis Analyzer
Event Tracing in Hardware
Event Trace Build Flow
Running the Design in Hardware and Capturing Trace Data at Run-Time
XSDB Flow
XRT Flow
Viewing and Analyzing the Trace Data Using Vitis Analyzer
Using Multiple Event Trace Streams
Troubleshooting Event Trace in Hardware
Programming the PS Host Application
Host Programming on Linux
Controlling the AI Engine Graph with the ADF API
Controlling the PL Kernel with the XRT API
Controlling the AI Engine Graph with the XRT C API
Controlling the AI Engine Graph with the XRT C++ API
Multi-Process and Multi-Thread Support for Controlling the AI Engine Graph
C++ XRT API for Multi-Process Support
Error Reporting Through the XRT API
AI Engine Error Events
Host Code Reference with ADF API and XRT API
Host Programming for Bare-Metal Systems
Addressing Kernels in Bare-metal Applications
Integrating the Application Using the Vitis Tools Flow
Platforms
PL Kernels
Compiling PL Kernels
Clocking the PL Kernels
Linking the System
Compile the Embedded Application for the Cortex-A72 Processor
Packaging
Packaging the System
Building a Bare-metal System
Running the System in Hardware
Running Software Emulation
Running Hardware Emulation
Generating Traffic for Emulation
AXI Traffic Generators
Formatting Data with Traffic Generators in Python
Deploying the System
Using the Vitis IDE
Creating the AI Engine Graph Project and Top-Level System Project
Importing Source Files
Vitis Tools Template Examples
Building the AI Engine Graph
Viewing Microcode
Running and Analyzing the Graph
Single Kernel Development
Adding a PL Kernel Project to the System
Configuring the HW-Link Project
Adding a PS Application to the System
Building and Running the System
Building a Bare-metal AI Engine in the Vitis IDE
Programming Device and Flash Memory
Debugging the AI Engine Application
Launching Debug from the Vitis IDE
Using printf for Event Tracing
Software Emulation Debug from the Vitis IDE
Vitis IDE Layout for Software Emulation Debug
Hardware Emulation Debug from the Vitis IDE
Hardware Debug from the Vitis IDE
Bare-Metal Debug from the Vitis IDE
Launching Debug from the Command Line
Software Emulation from Command Line
Hardware Emulation Debug from the Command Line
Debugging Only the AI Engine Graph
Hardware Debug from the Command Line
Debugging Only the AI Engine Hardware
Using the Debug Environment
Watchpoints
Viewing Data from Window Interfaces
Viewing Data from Stream Interfaces
Pipeline View for Single Kernel Debug
Mapper/Router Methodology
Design Convergence
Mapping Solution Not Found
Checking User-Defined Constraints
Reducing Window Buffer Sizes for Very High Memory Density Designs
Providing User Guidance to Mapper
Routing Solution Not Found
FIFO Depth Constraints
Area Group Constraints
Checking Mapping Results
Improving Design Performance
Memory Stalls
Stream Stalls
Large Skew Between Identical Graph Outputs
Adaptive Data Flow Graph Specification Reference
Return Code
Graph Objects
graph
kernel
port<T>
parameter
bypass
Graph Objects for Packet Processing
Platform Objects
platform<#in,#out>
FileIO
GMIO
PLIO
Event API
Enumeration
Member Functions
Connections
Connection Constructor Templates
Port Combinations
Constraints
constraint<T>
constraint< std::vector<T>>
Mapping Constraints
JSON Constraints
Node Constraints
Tile Constraint
Shim Constraint
Reserved Memory Constraint
Colocated Nodes Constraint
Not Colocated Nodes Constraint
Colocated Reserved Memories Constraint
Not Colocated Reserved Memories Constraint
Port Constraints
Buffers Constraint
Colocated Nodes Constraint
Not Colocated Nodes Constraint
Colocated Ports Constraint
Not Colocated Ports Constraint
Exclusive Colocated Ports Constraint
Colocated Reserved Memories Constraint
Not Colocated Reserved Memories Constraint
FIFO Constraint
Global Constraints
Area Group Constraint
IsomorphicGraphGroup Constraint
Event Trace Reference
Simulation Event Trace
Hardware Event Trace
Using the Restrict Keyword in AI Engine Kernels
Pointer Aliasing
Strict Aliasing Rule
Restrict Keyword
Restrict Qualification
Undefined Behavior
Scope of Restrict Keyword in Inline Function
Benefits of Using the Restrict Keyword for Read/Modify/Write Loops
Derived Pointers
Summary
Non-Templated Versions of Window and Stream APIs
Window Operations for Kernels
Window Data Types
Moving the Current Read/Write Position Forward
Moving the Current Read/Write Position Backward
Reading Data from an Input Window
Reading and Advancing an Input Window
Reading and Decrementing an Input Window
Writing Data to an Output Window
Writing and Advancing an Output Window
Stream Operations for Kernels
Stream Data Types
Reading and Advancing an Input Stream
Writing and Advancing an Output Stream
Using Streams in Parallel
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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