Vivado Design Suite User Guide: Using Constraints (UG903) - 2022.2 English

Document ID: UG903
Release Date: 2022-11-02
Version: 2022.2 English

Introduction
Migrating From UCF Constraints to XDC Constraints
Navigating Content by Design Process
About XDC Constraints
Constraints Methodology
About Constraints Methodology
Organizing Your Constraints
Project Flows
Non-Project Flows
Out-of-Context Constraints
Synthesis and Implementation Constraint Files
Ordering Your Constraints
Recommended Constraints Sequence
Constraints Sequence Editing
Constraint Files Order
Constraint Files Order with IP Cores
Changing Read Order
Entering Constraints
Saving Constraints in Memory
Constraints Editing Flow Options
User Interface Option
Hand Edit Option
Pin Assignment
Floorplanning
Timing Constraints Wizard
Constraints Processing Order and Invalid Constraints
Reporting Features Available When the Wizard is Open
Constraints Editing within the Wizard
Constraints Recommended by the Wizard
Primary Clocks
Generated Clocks
Forwarded Clocks
External Feedback Delays
Input Delays
Output Delays
Combinatorial Delays
Physically Exclusive Clock Groups
Logically Exclusive Clock Groups with No Interaction
Logically Exclusive Clock Groups with Interaction
Asynchronous Clock Domain Crossings
Recommended Asynchronous Clock Groups Constraints
Non-Recommended Asynchronous Clock Groups Constraints
CDC Synchronizers and ASYNC_REG Property
Completing the CDC Analysis and Constraints
Constraints Summary
Timing Constraints Window
Timing Constraints Spreadsheet
Constraints Creation, Grouped by Category
All Constraints
XDC Templates
XDC Template Contents
Using XDC Templates
Advanced XDC Templates
Creating Synthesis Constraints
RTL Attributes
Timing Constraints
Physical and Configuration Constraints
Elaborated Design Constraints
Single-Bit Register Names
Multi-Bit Register Names
Absorbed Registers and Nets
Hierarchical Names
Creating Implementation Constraints
Constraints and Object Queries
Adjusting Constraints for Synthesis Logic Replication
Adjust Constraints for Synthesis with Black-Boxes
Constraints Scoping
XDC File Scoping Properties
Setting XDC File Scoping Properties Example
XDC Scoping Mechanism
IP and Sub-Module Constraining with XDC
Scoped Queries Guidelines
Scoped Timing Constraints Guidelines
Recommended Constraints Rules of IP/Sub-Module XDC
Constraints Efficiency
Reviewing Constraints Coverage
Improving Constraints Runtime
Optimizing Pin Queries
Replacing all_registers Queries
Ordering Constraints for Better Runtime
Defining Clocks
About Clocks
Propagated Clocks
Dedicated Hardware Resources
Primary Clocks
Primary Clocks Examples
Virtual Clocks
Generated Clocks
About Generated Clocks
User Defined Generated Clocks
Example One: Simple Division by 2
Example Two: Division by 2 With the -edges Option
Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options
Example Four: Using Both -divide_by and -multiply_by at the Same Time
Example Five: Tracing the Master Clock through Combinational Arcs Only
Example Six: Forwarded Clock Driven by ODDR
Automatically Derived Clocks
Automatically Derived Clock Example
Local Net Names
Name Conflicts
Renaming Auto-Derived Clocks
Limitations
Clock Groups
About Clock Groups
Clock Categories
Synchronous Clocks
Asynchronous Clocks
Unexpandable Clocks
Asynchronous Clock Groups
Creating Asynchronous Clock Groups
Exclusive Clock Groups
Exclusive Clock Groups Example
Clock Latency, Jitter, and Uncertainty
Clock Latency
Clock Uncertainty
Clock Jitter
Input Jitter
System Jitter
Additional Clock Uncertainty
Constraining I/O Delay
About Constraining I/O Delay
Input Delay
Using Input Delay Options
Min and Max Input Delay Command Options
Clock Fall Input Delay Command Option
Add Delay Input Delay Command Option
Use of set_input_delay Command Options
Output Delay
Using Output Delay Options
Min and Max Output Delay Command Options
Clock Fall Output Delay Command Option
Add Delay Output Delay Command Option
Use of set_output_delay Command Options
Timing Exceptions
About Timing Exceptions
Multicycle Paths
Setting the Path Multipliers and Clock Edges
set_multicycle_path Syntax
Multicycles in Single Clock Domain
Relaxing Setup While Maintaining Hold
Moving the Setup
Example One: Setup=5 / Hold Moved Accordingly
Example Two: Setup=5 / Hold=4
Multicycle Paths and Clock Phase-Shift
Multicycles Between SLOW-to-FAST Clocks
Example One: Setup=3 / Hold Moved Accordingly
Example Two: Setup=3 / Hold=2 (-end)
Multicycles Between FAST-to-SLOW Clocks
Example: Setup=3 (-start) / Hold=2
False Paths
Min/Max Delays
Setting Maximum Delay and Minimum Delay Constraints
List of Nodes for the -from Option
List of Nodes for the -to Option
List of Nodes for the -through Option
Consequences of Setting Maximum Delay or Minimum Delay Constraints on a Path
Constraining Input or Output Logic
Constraining Asynchronous Signals
Path Segmentation
Path Segmentation and Timing Exception
Case Analysis
Disabling Timing Arcs
CDC Constraints
About CDC Constraints
Constraining Bus Skew
About Bus Skew Constraints
Syntax of the set_bus_skew Command
set_bus_skew Example One
set_bus_skew Example Two
Set Bus Skew Dialog Box
XDC Precedence
About XDC Precedence
XDC Constraints Order
Exceptions Priority
Exceptions Priority Example
Exceptions Priority with Multiple -through Options Example
Exceptions Priority with -reset_path Example
Physical Constraints
About Physical Constraints
Critical Warning
Netlist Constraints
CLOCK_DEDICATED_ROUTE
MARK_DEBUG
DONT_TOUCH
LOCK_PINS
I/O Constraints
Placement Constraints
Placement Types
Placement Constraint Examples
Routing Constraints
Fixed Routing
Configuration Constraints
Defining Relatively Placed Macros
About Relatively Placed Macros
Defining Sets of Design Elements
Creating an RPM
Assigning Cells to RPM Sets
Explicitly Grouping Design Elements
Explicitly Grouping Design Elements With U_SET
Explicitly Grouping Design Elements With HU_SET
Syntax for Defining RPM Sets in VHDL
Syntax for Defining RPM Sets in Verilog
RPM Definition in the Physical Constraints Window
Viewing RPM Definitions
Preserving RPM through opt_design
Assigning Relative Locations
Relative Slice-Based Coordinates
BEL/LOC Constraints
Absolute RPM Grid-Based Coordinates
RPM_GRID Coordinates VHDL Example
Setting a Property to Invoke the RPM_GRID System
RPM_GRID Coordinate Values
Defining RLOC Properties Directly in the RTL Source File
Assigning a Fixed Location to an RPM
XDC Macros
Specifying Macros
create_macro
update_macro
delete_macros
get_macros
Managing Macros
Macro Properties
Macro Properties Example
Preserving XDC Macros through opt_design
Advanced XDC Macro Examples
Relative Grid Macro Examples
Absolute Grid Macro Examples
Example: Assign the Variable rloc to the String Value of a Block RAM Cell RLOC
Example: Build an RLOC List for the Example Circuit
Converting RPMs to XDC Macros
Supported XDC and SDC Commands
Valid Commands in an XDC File
Supported SDC Commands
Unsupported SDC Commands
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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