Vivado Design Suite User Guide: Power Analysis and Optimization (UG907) - 2022.2 English

Document ID: UG907
Release Date: 2022-10-19
Version: 2022.2 English

Power in Xilinx Devices
Navigating Content by Design Process
Introduction
Power Terminology
Device Characterization
Signal Rate
Toggle Rate
Static Probability
Power Supplies in Xilinx Devices
Xilinx Device Power and the Overall Design Process
Power Estimation in System Design
Xilinx Power Estimation, Analysis, and Optimization Tools
Power Design Manager
Xilinx Power Estimator (XPE)
Vivado Power Analysis
Vivado Power Optimization
Power Budgeting
Estimating Power - Vivado Design Flow Stage
Introduction
Power Estimation Expectations
Analyzing Power in the Vivado Integrated Design Environment
Setting Up Power Analysis from the Vivado IDE
Running Power Analysis from the Vivado IDE
Vectorless Power Analysis
Vector (SAIF) Based Power Analysis
Specifying Switching Activity for Power Analysis
Review Device and Design Settings and Adjust Activity for Known Elements
Environment Tab
Power Supply Tab
Switching Tab
Output Tab
Run Power Analysis
Retaining the Switching Activity Constraints
Review Your Design Power Distribution
Alert for Maximum Package Current
Power Analysis of Zynq UltraScale+ RFSoC
Power Analysis of SD-FEC Core
Power Analysis of RF Converter
Power Analysis of Virtex UltraScale+ HBM
Power Analysis of Virtex UltraScale+ GTM
Power Analysis and Optimization in the Vivado Design Suite
Introduction
Power Analysis in the Vivado Integrated Design Environment
Supported Device Architecture
Supported Inputs
Supported Outputs
Further Refining Control Signal Activity
Analyzing Power Reports from the Vivado Integrated Design Environment
Setting Power and Current Budget for Xilinx Devices
Power Rail Creation and Management
Save and Restore Power Reports
Performing What If? Analysis in the Vivado Integrated Design Environment
Power Constraints Advisor
Deassertion of Resets
Viewing Switching Activity on Schematics
Power Analysis Using the Tcl Interface
Power Analysis Tcl Commands
Timing Constraints that Influence Power Analysis
Setting Up Power Analysis from the Tcl Prompt
Device Environment
Netlist Element Activity
set_case_analysis
Minimum Input Set
Running Power Analysis from the Tcl Prompt
Analyzing Power Reports from the Tcl Prompt
Use Model Examples
Example 1: Post-Synthesis and Post-Implementation Power Estimation and Comparison in Project Mode
Example 2: Post-Synthesis and Post-Implementation Power Estimation and Comparison in Projectless Mode
Example 3: Examine and ensure Static Probability values on resets are accurate
Example 4: What If? Design Analysis/Report, Edit, and Reset Design Activity
Power Optimization Feature
Block RAM WRITE_MODE Power Optimizations
Block RAM Cascade Optimizations
Performing Power Optimization in the Vivado Integrated Design Environment
Displaying a Power Optimization Report in the Vivado IDE
Performing Power Optimization Using the Tcl Interface
Setting Power Optimization Constraints
Running Power Optimization
Generating a Power Optimization Text Report
Guidelines to Maximize Power Saving with Power Optimization
Preserving Timing After Power Optimization
Achieving an Accurate Power Analysis Using Vivado Report Power
Introduction
Thermal Settings
Process Corners
Junction Temperature
Power Supply Settings
Clock Specifications
Control Signals
Global and Regional Resets
Global Clock Enables
Primary Inputs
Component Level
Versal ACAP and Report Power
Introduction to Versal ACAP
Report Power for Versal ACAP
AI Engine
AI Engine-ML
Network on Chip (NoC)
DDR Memory Controller (DDRMC)
MRMAC
DCMAC
Interlaken
PCIe
DSP
PS-PMC
IO
CPM
GTY
GTM
Tips and Techniques for Power Reduction
Introduction
System-Level Power Reduction
Cooling Strategy
Supply Strategy
Device Selection
Measuring Power and Temperature
Power Measurement Techniques
Using a Current Sense Resistor
Using Advanced Regulators and Digital Power Controllers
Performing On-Board Monitoring
Having Separate Voltage Rails
Thermal Measurement Techniques
Performing External Monitoring
Performing On-Board Monitoring
Methodology for Power and Temperature Measurement
Device Static
Design Static
Design Dynamic
Design Level Power Reduction
Further Optimizing the Design After it Meets Constraints
My Power Budget is Exceeded! What Can I Do?
Step 1: Which Power Budget is Exceeded?
Step 2: Identify the Area on Which to Focus
Step 3: Experiment
Use Device Resources More Efficiently
Experiment Using the Vivado Power Optimizer Feature
Experiment within the Vivado Power Analysis Feature
Experiment within Xilinx Power Estimator (XPE)
Experiment within RTL Code
Step 4: Implement the Changes and Review the Power Saving
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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