AI Engine Tools and Flows User Guide (UG1076) - 2023.1 English

Document ID: UG1076
Release Date: 2023-06-23
Version: 2023.1 English

Overview
Navigating Content by Design Process
AI Engine Architecture Overview
AI Engine Components
Tools
Documentation
Compiling an AI Engine Graph Application
Setting Up the Vitis Tool Environment
Inputs
Outputs
AI Engine Compiler Options
Mapper and Router Options
Viewing Compilation Results in the Vitis Analyzer
Graph and Array Details
Kernels
I/O
Buffers
Ports
Nets
Tiles
Interface Channels
Compilation Summary
AI Engine Compiler Guidance
Simulating an AI Engine Graph Application
x86 Functional Simulator
Compiling the Design
Simulator Options
Data Snapshots
Deadlock Detection
Trace Report
Memory Access Violations and Valgrind
Using GDB
Macros
Printf() Macros
Using printf() in Kernels
Limitations
Memory Model
Graph API Calls
Preprocessor Considerations
Packet Switching and RTP
Packet Switching
Synchronous and Asynchronous RTP
Best Practices
Software Emulation
Reusing x86 Simulator Options
AI Engine SystemC Simulator
Simulator Options
Simulation Input and Output Data Streams
Simulating Global Memory
Hardware Emulation
Reusing AI Engine Simulator Options
Enabling Third-Party Simulators
External Traffic Generator
Performance Analysis of AI Engine Graph Application during Simulation
Analyzing AI Engine Status in Hardware Emulation
AI Engine Simulation-Based Performance Analysis
AI Engine Simulation-Based Profiling
AI Engine Simulation-Based Value Change Dump
VCD File Generation
AI Engine Trace from VCD
Generating VCD with Select Signals
Vitis IDE to Enable Selective VCD File Generation
Viewing the Run Summary in the Vitis Analyzer
Trace View Data Visualization
Window Data Analysis
Supported Window Data Types
Stream Data Analysis
Supported Stream Data Types
Cascade Data Analysis
Scalar RTP Data Analysis
Data Display Limitations
Cross Probing
Trace Compare
AI Engine Stall Analysis in Vitis Analyzer
Performance Metrics
Lock Stall Analysis
Stream Stall Analysis
Cascade Stall Analysis
Memory Stall Analysis
FIFO Depth Visualization in Vitis Analyzer
DMA FIFO Depth Visualization
Stream Switch FIFO Visualization
Using Trace Compass to Visualize AI Engine Traces
Trace Views
Performance Analysis of AI Engine Graph Application on Hardware
Analyzing AI Engine Status in Hardware
Generating AI Engine Status
Analyzing AI Engine Status in Vitis Analyzer
Deadlock Detection using XSDB
Profiling the AI Engine
Profiling the AI Engine in Hardware
Profiling the AI Engine, Memory Modules and Interface Tiles
Profiling for AI Engine
Profiling for Memory Modules
Profiling for Interface Tiles
Metric Sets
Profiling Flows
XSDB Flow
XRT Flow
Viewing Profiling Results Using Vitis Analyzer
Event Profile APIs for Graph Inputs and Outputs
Profiling Running Event and Graph Throughput
Profiling Graph Throughput
Profiling Graph Latency
Profiling Graph Bandwidth
Run-Time Event API Performance Counters Usage Summary
Event Tracing in Hardware
Event Trace Build Flow
Running the Design in Hardware and Capturing Trace Data at Run-Time
XSDB Flow
XRT Flow
Viewing and Analyzing the Trace Data Using Vitis Analyzer
Using the Delayed Event Trace
Using Multiple Event Trace Streams
Troubleshooting Event Trace in Hardware
Viewing Guidance Using Vitis Analyzer
Programming the PS Host Application
Host Programming on Linux
Controlling the Application with the XRT C++ API
Controlling AI Engine GMIO Transfers
Multi-Process and Multi-Thread Support for Controlling the AI Engine Graph
AI Engine Error Reporting
AI Engine Error Events
Compiling and Linking Host Code for Linux
Host Programming for Bare-Metal
Addressing Kernels in Bare-Metal Applications
Compiling and Linking Host Code for Bare-Metal
Host Programming Support Comparison Between Linux and Bare-Metal
Resetting and Reloading Flow of the AI Engine Array
Generate AI Engine-only and PL-only XCLBIN
Host Application for Reset and Reload Flow
Reset Before Consecutive Application Runs
Integrating the Application Using the Vitis Tools Flow
Platforms
PL Kernels
Compiling PL Kernels
Clocking the PL Kernels
Linking the System
Compiling the Embedded Application for the Cortex-A72 Processor
Compiling the Embedded Application for the x86 Processor
Iterative AI Engine Application Compilation
Packaging
Packaging the System for Hardware
Packaging the System for Software
Building a Bare-Metal System
Running the System in Hardware
Running Software Emulation
Running Hardware Emulation
Generating Traffic for Simulation and Emulation
AXI Traffic Generators
Creating Traffic Generators in Python and C++
Creating Traffic Generators using System Verilog/Verilog
Deploying the System
Targeting the DFX Platform
Using the Vitis IDE
Creating the AI Engine Graph Project and Top-Level System Project
Importing Source Files
Vitis Tools Template Examples
Building the AI Engine Graph
Viewing Microcode
Running and Analyzing the Graph
Single Kernel Development
Adding a PL Kernel Project to the System
Configuring the HW-Link Project
Adding a PS Application to the System
Building and Running the System
Building a Bare-metal AI Engine in the Vitis IDE
Programming Device and Flash Memory
Debugging the AI Engine Application
Launching Debug from the Vitis IDE
Using printf for Event Tracing
Software Emulation Debug from the Vitis IDE
Vitis IDE Layout for Software Emulation Debug
Hardware Emulation Debug from the Vitis IDE
Hardware Debug from the Vitis IDE
Bare-Metal Debug from the Vitis IDE
Launching Debug from the Command Line
Running Software Emulation from the Command Line
Hardware Emulation Debug from the Command Line
Debugging Only the AI Engine Graph
Hardware Debug from the Command Line
Debugging Only the AI Engine Hardware
Using the Debug Environment
Watchpoints
Viewing Data from Buffer Port Interfaces
Viewing Data from Stream Interfaces
Pipeline View for Single Kernel Debug
Mapper/Router Methodology
Design Convergence
Mapping Solution Not Found
Checking User-Defined Constraints
Reducing Window Buffer Sizes for Very High Memory Density Designs
Providing User Guidance to Mapper
Routing Solution Not Found
FIFO Depth Constraints
Area Group Constraints
Relative Constraints
Checking Mapping Results
Improving Design Performance
Memory Stalls
Stream Stalls
Large Skew Between Identical Graph Outputs
AI Engine Hardware Profile and Debug Methodology
Overview of Versal System Profile and Validation Methodology
Hardware Profile and Debug Methodology
Stage 1: Design Execution and System Metrics
Stage 2: System Profiling
Stage 3: PL Kernel Analysis
Stage 4: AI Engine Event Trace and Analysis
Stage 5: Host Application Debug
Summary
Event Trace Reference
Simulation Event Trace
Hardware Event Trace
Encrypting AI Engine Kernels
Introduction to the new Vitis Unified IDE
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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