Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387) - 2023.1 English

Document ID: UG1387
Release Date: 2023-05-24
Version: 2023.1 English

Introduction
About the Versal Adaptive SoC Design Methodology
Navigating Content by Design Process
System Design Types
Design Flows
Design Flow Diagrams
Traditional Design Flows
Traditional Design Flow for Hardware-Only Systems
Traditional Design Flow for Embedded Systems
Platform-Based Design Flows
Platform-Based Design Flow Best Practices
Understanding Versal Adaptive SoC Design Methodology Concepts
Creating and Implementing a Hardware Design
Maximizing Impact Early in the Development Cycle
Validating at Each Design Stage
Using the Versal Adaptive SoC Design Methodology DRCs
Using the Vivado Design Suite
Managing Vivado Design Suite Sources with a Revision Control System
Upgrading to New Vivado Design Suite Releases
Using the Vitis Environment
About This Guide
Design Planning
Design Planning for Key IP Blocks
Design Planning Considerations for the Traditional Design Flow
Design Planning Considerations for the Platform-Based Design Flow
Design Planning Considerations for Dynamic Function eXchange
Design Planning Considerations for DFX-based Vitis Acceleration Platform Development
Design Planning Considerations for Tandem Configuration
Design Creation with Block Designs
Defining a Good Block Design Hierarchy
Methods for Using Block Designs with IP Integrator
Instantiating Block Designs
Using Different Source Files in IP Integrator
Custom Packaged IP
Packaged Block Designs
Block Design Containers
RTL Module References
Block Design Comparison
Block Design Updates
Recommendations for Designing with Versal Device IP
Recommendations for Different Versal Device Design Topologies
Creating a Hardware Platform for the Platform-Based Design Flow
Design Creation with RTL
Defining a Good RTL Design Hierarchy
Add I/O Components Near the Top Level
Insert Clocking Elements Near the Top Level
Register Data Paths at Logical Boundaries
Optimize Hierarchy for Functional and Timing Debug
Apply Attributes at the Module Level
Optimize Hierarchy for Advanced Design Techniques
Example of Upfront Hierarchical Planning for High Speed DSP Designs
Working with Intellectual Property (IP)
Planning IP Requirements
AMBA AXI
Vivado Design Suite IP Catalog
Custom IP
Selecting IP from the IP Catalog
Customizing IP
Using the Customization GUI
Using a Tcl Script
IP Versions and Revision Control
RTL Coding Guidelines
Using Vivado Design Suite HDL Templates
Control Signals and Control Sets
Resets
When and Where to Use a Reset
Synchronous Reset vs. Asynchronous Reset
Reset Coding Example: Multiplier Pipeline Registers with Synchronous and Asynchronous Reset
Issues When Trying to Eliminate Reset in HDL Code
Clock Enables
Creating Clock Enables
Reset and Clock Enable Precedence
Controlling Enable/Reset Extraction with Synthesis Attributes
Using DIRECT_ENABLE and DIRECT_RESET
Pushing the Logic from the Control Pin to the Data Pin
Tips for Control Signals
Know What You Infer
Inferring RAM and ROM
Performance Considerations When Implementing RAM
Scenarios Preventing Block RAM Output Register Inference
Checking for Multi-Fanout on the Output of Read Data Registers
Checking for Reset Signals on the Address/Read Data Registers
Checking for Feedback Structures in Registers
Mapping Memories to UltraRAM Blocks
Coding for Optimal DSP and Arithmetic Inference
Coding Shift Registers and Delay Lines
Initialization of All Inferred Registers, SRLs, and Memories
Deciding When to Instantiate or Infer
Synthesis Tool Optimization
When Instantiation Is Desirable
Coding Styles to Improve Maximum Frequency
High Fanouts in Critical Paths
Reduce Loads in Portions of the Design That Do Not Require It
Replicate High Fanout Net Drivers
Pipelining Considerations
Consider Pipelining Up Front
Check Inferred Logic
Determine Whether Pipelining is Needed
Balance Latency
Balance Pipeline Depth and SRL Usage
Avoid Unnecessary Pipelining
Consider Pipelining Macro Primitives
Auto-Pipelining Considerations
Coding Styles to Improve Power
Gate Clock or Data Paths
Maximize Gating Elements
Use Clock Enable Pins of Dedicated Clock Buffers
Use Case Block When Priority Encoder Not Needed
Performance/Power Trade-Off for Block RAMs
Decomposing Deeper Memory Configurations for Balanced Power and Clock Frequency
Running RTL DRCs
Coding for FIFOs
Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow
Kernel Types
Kernel Interfaces
Design Recommendations for RTL Kernels
Packaging RTL Kernels
Kernel Debug and Verification Considerations
Clocking Guidelines
Versal Device Clocking
Clock Primitives
Global Clock Buffer Connectivity and Routing Tracks
Clock Routing, Root, and Distribution
Clock Tree Placement and Routing
Topologies with and without Placement Rules
Clocking Capability
High Fanout Clocks
Low Fanout Clocks
Clock Constraints
Using LOC Constraints for IO/MMCM/XPLL/DPLL/GT
Using the CLOCK_REGION Property on Global Clock Buffers
Using the GCLK_DESKEW Property on a Clock Net
Using the CLOCK_LOW_FANOUT Constraint
Using the USER_CLOCK_ROOT Property on a Clock Net
Using the CLOCK_DELAY_GROUP Constraint on Several Clock Nets
Using the CLOCK_DEDICATED_ROUTE Constraint
Using the CLOCK_ROUTE_GUIDE Constraint
Clocking Topology Recommendations
MBUFG Primitives
Parallel Clock Buffers
Cascaded Clock Buffers
Clock Multiplexing
MMCM Feedback Path and Compensation Mode
Fabric Clocks Sourced from GTs
USER_CLOCK_ROOT Assignment
Optimal CLOCK_ROOT Placement
Improving Fmax Guidance
Avoid GT Column When Clock Crosses SLRs
Center Clock Root in Horizontal Direction
Clock Phase Shift Modeling
PLL/MMCM Inverted Clocks
SelectIO I/O Logic Clocking
IDDRE1 Clocking
Synchronous CDC
GT Interface Clocking
XPIO Global Clock Buffer Clock Enable Timing
Designing the Clock Structure
Inference
Synthesis Constraints and Attributes
Use of IP
Instantiation
Controlling the Phase, Frequency, Duty-Cycle, and Jitter of the Clock
Using Clock Modifying Blocks (MMCM, XPLL, and DPLL)
Using Gated Clocks
Converting Clock Gating to Clock Enable
Gating the Clock Buffer
Controlling and Synchronizing Device Startup
Avoiding Local Clocks
Creating an Output Clock
Clocking Recommendations for Platforms and Dynamic Function eXchange
DFX Behavior for Clock Nets
Reconfigurable Module Internal Clock Nets
Boundary Clock Nets
DFX Clocking Enhancements for Versal Adaptive SoC
Clock Routing Tile Sharing Between Reconfigurable Partitions in DFX
MBUFG Primitive Usage Rules in DFX Designs
Clock Domain Crossing
Single-Bit CDC
Multi-Bit CDC
Constraining the Design Correctly
Design Creation with Vitis HLS
Vitis HLS Methodology
Defining Interfaces
Using Vitis HLS in the Vitis Kernel Flow
Vitis HLS Principles for Software Programmers
Designing Efficient Kernels
Interfacing HLS Kernels to AI Engine Graphs
Interfacing HLS Kernels to the NoC
Optimization Techniques in Vitis HLS
Vitis HLS Debug and Verification Considerations
I/O Planning Design Flows
Types of Vivado Design Suite Projects for I/O Planning
Pre-RTL I/O Planning
Netlist-Based I/O Planning
Required Information for Pin Assignment
Pinout Selection
General Pinout Selection Guidelines
Platform Management Controller Pins
Memory and Advanced I/O Interfaces
Gigabit Transceivers (GTs)
Corner Banks
Interface Bandwidth Validation
SSI Technology Considerations for I/O Planning
Designing with SSI Devices
SSI Pinout Considerations
Super Logic Region (SLR)
SLR Nomenclature
Silicon Interposer
Super Long Line (SLL) Routes
Propagation Limitations
SLR Utilization Considerations
SLR Utilization Example
SLR Crossing for Wide Buses
NoC Considerations
Designing with HBM Devices
Placement Considerations When Using HBM Devices
Pipelining Considerations for Crossing SLRs
Resource Planning within Top SLR
Using NoC Connectivity for Critical Connections Farther from the Stacks
Design Constraints
Organizing the Design Constraints for Compilation
Recommended Constraint Files
Simple Design
Complex Design
Validating the Read Sequence
Recommended Constraints Sequence
Creating Synthesis Constraints
Creating Implementation Constraints
Creating Block-Level Constraints
Specifying Constraints for the Vitis Environment
Defining Timing Constraints
Defining Timing Constraints in Four Steps
Defining Clock Constraints
Identifying Clock Sources
Clock Networks Report
Check Timing Report
Creating Primary Clocks
Input Ports
Certain Hardware Primitive Output Pins
Creating Generated Clocks
Auto-Derived Clocks
User-Defined Generated Clocks
Path Between Master and Generated Clocks
Verifying Clocks Definition and Coverage
Adjusting Clock Characteristics
Jitter
Additional Uncertainty
Clock Latency at the Source
MMCM External Feedback Loop Delay
Constraining Input and Output Ports
System Level Perspective
Defining Input Delays
Defining Output Delays
Choosing the Reference Clock
Identifying the Clocks Related to Each Port
Browse the Board Schematics
Browse the Design Schematics
Report Timing from or to the Port
Use Automatically Identified Sampling Clocks
Using a Primary Clock
Using a Virtual Clock
Using a Generated Clock
Rising and Falling Reference Clock Edges
Verifying Delay Constraints
I/O Path Report Command Lines Example
Input to Output Feed-through Path
Example One
Example Two
Using XDC Templates - Source Synchronous Interfaces
Defining Clock Groups and CDC Constraints
Reviewing Clock Interactions
Synchronous
Asynchronous
Exclusive
Categorizing Clock Pairs
Clock Interaction Report
Check Timing Report
Constraining Exclusive Clock Groups
Overlapping Clocks Defined on the Same Clock Source
Overlapping Clocks Driven by a Clock Multiplexer
Constraining Asynchronous Clock Groups and Clock Domain Crossings
Report CDC
Global Constraints Between Clocks in Both Directions
Constraints on Individual CDC Paths
Clock Exceptions Precedence Over set_max_delay
Specifying Timing Exceptions
Timing Exceptions Guidelines
Timing Exceptions Precedence and Priority Rules
Adding False Path Constraints
Use Cases
Impact on Implementation
Impact on Synthesis
Impact on Implementation
Adding Min and Max Delay Constraints
Use Cases
Impact on Synthesis
Impact on Implementation
Avoiding Path Segmentation
Valid Startpoints and Endpoints
Adding Multicycle Path Constraints
Relaxing the Setup Requirement While Keeping Hold Unchanged
Impact on Synthesis and Implementation
Common Mistakes
Other Advanced Timing Constraints
Case Analysis
Disable Timing
Data Check
Max Time Borrow
Specifying the RAM Activity for Jitter
Defining Power and Thermal Constraints
Defining Physical Constraints
Using the Boundary Logic Interface Constraint
Floorplanning Constraints for Dynamic Function eXchange
Design Implementation
Running Synthesis
Synthesis Flows
Global Synthesis
Block Design Synthesis
Out-of-Context Synthesis
Incremental Synthesis
Synthesis Optimizations
Synthesis Settings
Synthesis Attributes
KEEP and DONT_TOUCH
MAX_FANOUT
Block-Level Synthesis Strategy
Moving Past Synthesis
Reviewing and Cleaning DRCs
Running Report Methodology
Reviewing the Synthesis Log
Reviewing Timing Constraints
Assessing Post-Synthesis Quality of Results
Following Guidelines to Address Remaining Violations
Dealing with High Levels of Logic
Reviewing Utilization
Reviewing Clock Trees
Clock Buffer Utilization
Clock Tree Topology
Implementing the Design
Using Project Mode vs. Non-Project Mode
Strategies
Directives
Iterative Flows
Analyzing a Design at Different Stages Using Checkpoints
Using Interactive Report Files
Using Incremental Implementation Flows
Automatic Incremental Implementation Mode
Incremental Directives and Target WNS
Configuring the Incremental Flow
Parallel Runs
Compile Time Considerations
Opening the Synthesized Design
Logic Optimization (opt_design)
Optimization Analysis
Placement (place_design)
Placement Analysis
NoC Compiler Runs During Placement
Physical Optimization (phys_opt_design)
Need for Physical Synthesis
Routing (route_design)
Route Analysis
Route Compile Time
Embedded Platform Creation for the Vitis Environment
Mapping Functionality to the Platform and the Subsystem
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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