Fast Partial Reconfiguration Over PCI Express (XAPP1338)

Document ID: XAPP1338
Release Date: 2019-03-11
Revision: 1.0 English

Summary
Introduction
Reference Design
Reference Design Matrix
Setup
Set the Frequency of the ICAP Clock
Block Diagrams
XDMA PCIe IP
Compile the Reference Design
Configure the Device via JTAG
Configure the Device via Dual QSPI
Connect to PCIe Host and Partially Reconfigure the FPGA
Use Debug Cores to Monitor Activity
Conclusion
Supported Features
Unsupported Features
Known Limitations
References
Revision History
Please Read: Important Legal Notices

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