Supported Attributes - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID: UG901
Release Date: 2023-06-09
Version: 2023.1 English

Vivado Synthesis
Introduction
Synthesis Methodology
Using Synthesis
Using Synthesis Settings
Tcl Commands to Get Property
Creating Run Strategies
Setting Synthesis Inputs
Controlling File Compilation Order
Defining Global Include Files
RTL Linter
Running the Linter
Linter Output
Creating Waivers for the RTL Linter
Running Synthesis
Using the Design Runs Window
Setting the Active Run
Launching a Synthesis Run
Setting a Bottom-Up, Out-of-Context Flow
Manually Setting a Bottom-Up Flow and Importing Netlists
Creating a Lower-Level Netlist
Instantiating the Lower-Level Netlist in a Design
Putting Together the Manual Bottom-Up Components
Incremental Synthesis
Setting Up Incremental Synthesis in Project Mode
Using Incremental Synthesis in Non-Project Mode
Interpreting the Log File
Re-Synthesizing the Full Design
Using Third-Party Synthesis Tools with Vivado IP
Moving Processes to the Background
Monitoring the Synthesis Run
The following Synthesis
Analyzing Synthesis Results
Using the Synthesized Design Environment
Exploring the Logic
Exploring the Logic Hierarchy
Exploring the Logical Schematic
Running Timing Analysis
Running Synthesis with Tcl
Multi-Threading in RTL Synthesis
Tcl Script Example
Setting Constraints
Vivado Preconfigured Strategies
Synthesis Attributes
Introduction
Supported Attributes
ASYNC_REG
ASYNC_REG Verilog Example
ASYNC_REG VHDL Examples
BLACK_BOX
BLACK_BOX Verilog Example
BLACK_BOX VHDL Example
CASCADE_HEIGHT
CASCADE_HEIGHT Verilog example
CASCADE_HEIGHT VHDL example
CLOCK_BUFFER_TYPE
CLOCK_BUFFER_TYPE Verilog example
CLOCK_BUFFER_TYPE VHDL example
CLOCK_BUFFER_TYPE XDC Example
DIRECT_ENABLE
DIRECT_ENABLE Verilog Example
DIRECT_ENABLE VHDL Example
DIRECT_ENABLE XDC Example
DIRECT_RESET
DIRECT_RESET Verilog Example
DIRECT_RESET VHDL Example
DIRECT_RESET XDC Example
DONT_TOUCH
DONT_TOUCH Verilog Examples
Verilog Wire Example
Verilog Module Example
Verilog Instance Example
DONT_TOUCH VHDL Examples
VHDL Signal Example
VHDL Entity Example
VHDL Component Example
VHDL Example on Architecture
DSP_FOLDING
DSP_FOLDING Verilog Example
DSP_FOLDING VHDL Example
DSP_FOLDING_FASTCLOCK
DSP_FOLDING_FASTCLOCK Verilog Example
DSP_FOLDING_FASTCLOCK VHDL Example
EXTRACT_ENABLE
EXTRACT_ENABLE Verilog Example
EXTRACT_ENABLE VHDL Example
EXTRACT_ENABLE XDC Example
EXTRACT_RESET
EXTRACT_RESET Verilog Example
EXTRACT_RESET VHDL Example
EXTRACT_RESET XDC Example
FSM_ENCODING
FSM_ENCODING Verilog Example
FSM_ENCODING VHDL Example
FSM_SAFE_STATE
FSM_SAFE_STATE Verilog Example
FSM_SAFE_STATE VHDL Example
FULL_CASE (Verilog Only)
FULL_CASE Verilog Example
GATED_CLOCK
GATED_CLOCK Verilog Example
GATED_CLOCK VHDL Example
GATED_CLOCK XDC Example
IOB
IOB Verilog Example
IOB VHDL Example
IO_BUFFER_TYPE
IO_BUFFER_TYPE Verilog Example
IO_BUFFER_TYPE VHDL Example
KEEP
KEEP Verilog Example
KEEP VHDL Example
KEEP_HIERARCHY
KEEP_HIERARCHY Verilog Example
KEEP_HIERARCHY VHDL Example
KEEP_HIERARCHY XDC Example
MARK_DEBUG
Syntax
Verilog Syntax
Verilog Syntax Example
VHDL Syntax
VHDL Syntax Example
XDC Syntax
XDC Syntax Example
MAX_FANOUT
MAX_FANOUT Verilog Example
MAX_FANOUT VHDL Example
PARALLEL_CASE (Verilog Only)
RAM_DECOMP
RAM_DECOMP Verilog Example
RAM_DECOMP VHDL Example
RAM_DECOMP XDC Example
RAM_STYLE
RAM_STYLE Verilog Example
RAM_STYLE VHDL Example
RETIMING_BACKWARD
RETIMING_BACKWARD Verilog Example
RETIMING_BACKWARD VHDL Example
RETIMING_BACKWARD XDC Example
RETIMING_FORWARD
RETIMING_FORWARD Verilog Example
RETIMING_FORWARD VHDL Example
RETIMING_FORWARD XDC Example
ROM_STYLE
ROM_STYLE Verilog Example
ROM_STYLE VHDL Example
RW_ADDR_COLLISION
RW_ADDR_COLLISION Verilog Example
RW_ADDR_COLLISION VHDL Example
SHREG_EXTRACT
SHREG_EXTRACT Verilog Example
SHREG_EXTRACT VHDL Example
SRL_STYLE
SRL_STYLE Verilog Example
SRL_STYLE VHDL Example
SRL_STYLE XDC Example
TRANSLATE_OFF/TRANSLATE_ON OFF/ON
TRANSLATE_OFF/TRANSLATE_ON OFF/ON Verilog Example
TRANSLATE_OFF/TRANSLATE_ON OFF/ON VHDL Example
USE_DSP
USE_DSP Verilog Example
USE_DSP VHDL Example
Custom Attribute Support in Vivado
Example with Custom Attribute on Hierarchy (Verilog)
Example with Custom Attribute on Hierarchy (VHDL)
Example with Custom Attribute on a Signal (Verilog)
Example with Custom Attribute on a Signal (VHDL)
Using Synthesis Attributes in XDC files
Synthesis Attribute Propagation Rules
Using Block Synthesis Strategies
Overview
Setting a Block-Level Flow
Block-Level Flow Options
HDL Coding Techniques
Introduction
Advantages of VHDL
Advantages of Verilog
Advantages of SystemVerilog
Flip-Flops, Registers, and Latches
Flip-Flops and Registers Control Signals
Coding Guidelines
Flip-Flops and Registers Inference
Flip-Flops and Registers Initialization
Flip-Flops and Registers Reporting
Flip-Flops and Registers Reporting Example
Flip-Flops and Registers Coding Examples
Register with Rising-Edge Coding Verilog Example
Flip-Flop Registers with Rising-Edge Clock Coding VHDL Example
Latches
Latches Reporting Example
Latch With Positive Gate and Asynchronous Reset Coding Verilog Example
Latch With Positive Gate and Asynchronous Reset Coding VHDL Example
Tristates
Tristate Implementation
Tristate Reporting Example
Tristate Description Using Concurrent Assignment Coding Verilog Example
Tristate Description Using Combinatorial Process Implemented with OBUFT Coding VHDL Example
Tristate Description Using Combinatorial Always Block Coding Verilog Example
Shift Registers
Static Shift Register Elements
Shift Registers SRL-Based Implementation
Shift Registers Coding Examples
32-Bit Shift Register Coding Example One (VHDL)
32-Bit Shift Register Coding Example Two (VHDL)
8-Bit Shift Register Coding Example One (Verilog)
32-Bit Shift Register Coding Example Two (Verilog)
SRL Based Shift Registers Reporting
Dynamic Shift Registers
Dynamic Shift Registers Coding Examples
32-Bit Dynamic Shift Registers Coding Verilog Example
32-Bit Dynamic Shift Registers Coding VHDL Example
Multipliers
Multipliers Implementation
DSP Block Implementation
Multipliers Coding Examples
Unsigned 16x24-Bit Multiplier Coding Verilog Example
Unsigned 16x16-Bit Multiplier Coding VHDL Example
Multiply-Add and Multiply-Accumulate
Multiply-Add and Multiply-Accumulate Implementation
Macro Implementation on DSP Block Resources
Complex Multiplier Examples
Complex Multiplier Verilog Example
Complex Multiplier Examples (VHDL)
Pre-Adders in the DSP Block
Pre-Adder Dynamically Configured Followed by Multiplier and Post-Adder (Verilog)
Pre-Adder Dynamically Configured Followed by Multiplier and Post-Adder (VHDL)
Using the Squarer in the UltraScale DSP Block
Square of a Difference (Verilog)
Square of a Difference (VHDL)
FIR Filters
8-Tap Even Symmetric Systolic FIR (Verilog)
8-Tap Even Symmetric Systolic FIR (VHDL)
Convergent Rounding (LSB Correction Technique)
Rounding to Even (Verilog)
Rounding to Even (VHDL)
Rounding to Odd (Verilog)
Rounding to Odd (VHDL)
RAM HDL Coding Techniques
Choosing Between Distributed RAM and Dedicated Block RAM
Memory Inference Capabilities
UltraRAM Coding Templates
Inferring UltraRAM in Vivado Synthesis
Overview of the UltraRAM Primitive
Description of the UltraRAM Primitive
Differences between UltraRAM and Block RAM
Using UltraRAM Inference
Attributes for Controlling UltraRAM
RAM_STYLE
RAM_STYLE Verilog Example
RAM_STYLE VHDL Example
CASCADE_HEIGHT
CASCADE_HEIGHT Verilog Example
CASCADE_HEIGHT VHDL Example
Inference Capabilities
Pipelining the RAM
Creating Pipeline Example 1: 8K x 72
Creating Pipeline Example 2 : 8K x 80
Creating Pipeline Example 3: 16K x 70 CASCADE_HEIGHT Set to 3
RAM HDL Coding Guidelines
Block RAM Read/Write Synchronization Modes
Distributed RAM Examples
Dual-Port RAM with Asynchronous Read Coding Verilog Example
Single-Port RAM with Asynchronous Read Coding Example (VHDL)
Single-Port Block RAMs
Single-Port Block RAM with Resettable Data Output (Verilog)
Single Port Block RAM with Resettable Data Output (VHDL)
Single-Port Block RAM Write-First Mode (Verilog)
Single-Port Block RAM Write-First Mode (VHDL)
Single-Port RAM with Read First (VHDL)
Single-Port Block RAM No-Change Mode (Verilog)
Single-Port Block RAM No-Change Mode (VHDL)
Simple Dual-Port Block RAM Examples
Simple Dual-Port Block RAM with Single Clock (Verilog)
Simple Dual-Port Block RAM with Single Clock (VHDL)
Simple Dual-Port Block RAM with Dual Clocks (Verilog)
Simple Dual-Port Block RAM with Dual Clocks (VHDL)
True Dual-Port Block RAM Examples
Dual-Port Block RAM with Two Write Ports in Read First Mode Verilog Example
Dual-Port Block RAM with Two Write Ports in Read-First Mode (VHDL)
Block RAM with Optional Output Registers (Verilog)
Block RAM with Optional Output Registers (VHDL)
Byte Write Enable (Block RAM)
Byte Write Enable—True Dual Port with Byte-Wide Write Enable (Verilog)
Byte Write Enable—True Dual Port READ_FIRST Mode (VHDL)
Byte Write Enable—WRITE_FIRST Mode (VHDL)
Byte-Wide Write Enable—NO_CHANGE Mode (Verilog)
Byte-Wide Write Enable—NO_CHANGE Mode (VHDL)
Asymmetric RAMs
Simple Dual-Port Asymmetric RAM When Read is Wider than Write (VHDL)
Dual-Port Asymmetric RAM When Read is Wider than Write (Verilog)
Simple Dual-Port Asymmetric RAM When Write is Wider than Read (Verilog)
Simple Dual Port Asymmetric RAM When Write Wider than Read (VHDL)
True Dual Port Asymmetric RAM Read First (Verilog)
True Dual Port Asymmetric RAM Read First (VHDL)
True Dual Port Asymmetric RAM Write First (Verilog)
True Dual Port Asymmetric RAM Write First (VHDL)
Initializing RAM Contents
Specifying RAM Initial Contents in the HDL Source Code
VHDL Coding Examples
Verilog Coding Example
Specifying RAM Initial Contents in an External Data File
Verilog Code Example
VHDL Code Example
Initializing Block RAM (Verilog)
Initializing Block RAM (VHDL)
Initializing Block RAM From an External Data File (Verilog)
Initializing Block RAM From an External Data File (VHDL)
3D RAM Inference
RAMs Using 3D Arrays
3D RAM Inference Single Port (Verilog)
3D RAM Inference Single Port (VHDL)
3D RAM Inference Simple Dual Port (Verilog)
3D RAM Inference - Simple Dual Port (VHDL)
3D RAM Inference True Dual Port (Verilog)
RAM Inference Using Structures and Records
RAM Inference Single Port Structure (Verilog)
RAM Inference Single Port Structure (VHDL)
RAM Inference - Simple Dual Port Structure (SystemVerilog)
RAM Inference - Simple Dual Port Record (VHDL)
RAM Inference True Dual Port Structure (SystemVerilog)
RAM Inference True Dual Port Record (VHDL)
Black Boxes
Black Box Verilog Example
Black Box VHDL Example
FSM Components
Vivado Synthesis Features
FSM Description
FSM Diagrams
FSM Registers
Auto State Encoding
One-Hot State Encoding
Gray State Encoding
Johnson State Encoding
Sequential State Encoding
FSM Example (Verilog)
FSM Example with Single Sequential Block (VHDL)
FSM Reporting
ROM HDL Coding Techniques
ROM Using Block RAM Resources (Verilog)
ROM Inference on an Array (VHDL)
VHDL Support
Introduction
Supported and Unsupported VHDL Data Types
Unsupported Data Types
VHDL Data Types
VHDL Predefined Enumerated Types
Supported Overloaded Enumerated Types
VHDL User-Defined Enumerated Types
User-Defined Enumerated Types Coding Example (VHDL)
Supported VHDL Types
VHDL Integer Types
VHDL Multi-Dimensional Array Types
Fully Constrained Array Type Coding Example
Array Declared as a Matrix Coding Example
Multi-Dimensional Array Signals and Variables Coding Examples
VHDL Record Types Code Example
VHDL Objects
Signals
Variables
Constants
Operators
Shift Operator Examples
VHDL Entity and Architecture Descriptions
VHDL Circuit Descriptions
VHDL Entity Declarations
Constrained and Unconstrained Ports
Buffer Port Mode
NOT RECOMMENDED Coding Example WITH Buffer Port Mode
Dropping Buffer Port Mode
RECOMMENDED Coding Example WITHOUT Buffer Port Mode
VHDL Architecture Declarations
VHDL Architecture Declaration Coding Example
VHDL Component Instantiation
Elements of Component Instantiation Statement
Component Instantiation (VHDL)
Recursive Component Instantiation
Recursive Component Instantiation Example (VHDL)
VHDL Component Configuration
VHDL GENERICS
Declaring Generics
GENERIC Parameters Example
VHDL Combinatorial Circuits
VHDL Concurrent Signal Assignments
Simple Signal Assignment Example
Concurrent Selection Assignment Example (VHDL)
Generate Statements
Using for-generate Statements
Example of for-generate Statement (VHDL)
Using if-generate Statements
Example of for-generate Nested in an if-generate Statement (VHDL)
Combinatorial Processes
Memory Elements
Sensitivity List
Missing Signals
Variable and Signal Assignments
Signal Assignment in a Process Example
Variable and Signal Assignment in a Process Example (VHDL)
Using if-else Statements
Example of if-else Statement (VHDL)
Using case Statements
Example of case Statement (VHDL)
Using for-loop Statements
Example of for-loop Statement (VHDL)
VHDL Sequential Logic
Sequential Process With a Sensitivity List Syntax
Asynchronous Control Logic Modelization
Clock Event Statements
Missing Signals
VHDL Sequential Processes Without a Sensitivity List
Sequential Process Using a Wait Statement Coding Example (VHDL)
Describing a Clock Enable in the wait Statement Example (VHDL)
Describing a Clock Enable After the Wait Statement Example (VHDL)
Describing Synchronous Control Logic
VHDL Initial Values and Operational Set/Reset
Initializing Registers Example One (VHDL)
Initializing Registers Example Two (VHDL)
VHDL Functions and Procedures
Function Declared Within a Package Example (VHDL)
Procedure Declared Within a Package Example (VHDL)
Recursive Functions Example (VHDL)
VHDL Assert Statements
VHDL Predefined Packages
VHDL Predefined Standard Packages
VHDL IEEE Packages
VHDL Legacy Packages
VHDL Predefined IEEE Real Type and IEEE Math_Real Packages
VHDL Real Number Constants
VHDL Real Number Functions
Defining Your Own VHDL Packages
Package Declaration Syntax
Accessing VHDL Packages
VHDL Constructs Support Status
VHDL RESERVED Words
VHDL-2008 Language Support
Introduction
Setting up Vivado to use VHDL-2008
Supported VHDL-2008 Features
Operators
Matching Relational Operators
Maximum and Minimum Operators
Shift Operators (rol, ror, sll, srl, sla and sra)
Unary Logical Reduction Operators
Mixing Array and Scalar Logical Operators
Statements
If-else- If and Case Generate
Sequential Assignments
Using case? Statements
Using select? Statements
Using Slices in Aggregates
Types
Unconstrained Element Types
Using boolean_vector and integer_vector Array Types
Miscellaneous
Reading Output Ports
Expressions in Port Maps
Using the process (all) Statement
Referencing Generics in Generic Lists
Generics in Packages
Generic Types in Entities
Functions in Generics
Relaxed Return Rules for Function Return Values
Extensions to Globally Static and Locally Static Expressions
Static Ranges and Integer Expressions in Range Bounds
Block Comments
VHDL-2019 Language Support
Introduction
Setting up Vivado to use VHDL-2019
Supported VHDL-2019 Features
Interfaces
Conditional Identifiers
64-bit Integers
Verilog Language Support
Introduction
Verilog Design
Verilog Functionality
Verilog-2001 Support
Verilog-2001 Variable Part Selects
Variable Part Selects Verilog Coding Example
Structural Verilog
Built-In Logic Gates
2-Input XOR Function Example
Half-Adder Example
Instantiating Pre-Defined Primitives
Instantiating an FDC and a BUFG Primitive Example
Verilog Parameters
Parameters Example (Verilog)
Parameter and Generate-For Example (Verilog)
Verilog Parameter and Attribute Conflicts
Verilog Usage Restrictions
Case Sensitivity
Blocking and Non-Blocking Assignments
Unacceptable Example One
Unacceptable Example Two
Integer Handling
Integer Handling in Verilog Case Statements
Integer Handling in Verilog Case Statements Example
Integer Handling in Concatenations
Verilog-2001 Attributes and Meta Comments
Verilog-2001 Attributes
Verilog Meta Comments
Verilog Meta Comment Support
Verilog Meta Comment Syntax
Verilog Meta Comment Syntax Examples
Verilog Constructs
Verilog System Tasks and Functions
Using Conversion Functions
Loading Memory Contents With File I/O Tasks
Supported Escape Sequences
Verilog Primitives
Gate-Level Primitive Syntax
Gate-Level Primitive Example
Unsupported Verilog Gate Level Primitives
Verilog Reserved Keywords
Behavioral Verilog
Variables in Behavioral Verilog
Variable Declarations Example
Initial Values
Assigning an Initial Value to a Register
Initial Values Example One
Initial Values Example Two
Arrays of Reg and Wire
Arrays Example One
Arrays Example Two
Multi-Dimensional Arrays
Multi-Dimensional Array Example One
Multi-Dimensional Array Example Two
Data Types
Supported Data Types
Net and Registers
Behavioral Data Types Example
Legal Statements
Expressions
Logical Operators
Supported Operators
Supported Expressions
Evaluating Expressions
Evaluated Expressions Based on Most Frequently Used Operators
Blocks
Modules
Module Declaration
Circuit I/O Ports
Behavioral Verilog Module Declaration Example One
Behavioral Verilog Module Declaration Example Two
Module Instantiation
Behavioral Verilog Module Instantiation Example
Continuous Assignments
Explicit Continuous Assignments
Implicit Continuous Assignments
Procedural Assignments
Combinatorial Always Blocks
Delay Time Control Statement
Event Control Time Control Statement
Using if-else Statements
Example of if-else Statement
Case Statements
Multiplexer Case Statement Example (Verilog)
Avoiding Priority Processing
For and Repeat Statements
Using For Statements
Repeat Statements
Using While Loops
Example of While Loop
Using Sequential Always Blocks
Sequential Always Block Examples
Using assign and deassign Statements
Assignment Extension Past 32-Bits
Tasks and Functions
Tasks and Functions Examples
Using Recursive Tasks and Functions
Example of Recursive Tasks and Functions
Using Constant Functions and Expressions
Example of Constant Functions
Example of Constant Expressions
Using Blocking and Non-Blocking Procedural Assignments
Blocking Procedural Assignment Syntax Example One
Blocking Procedural Assignment Syntax Example Two (Alternate)
Non-Blocking Procedural Assignment Syntax Example One
Non-Blocking Procedural Assignment Example Two
Verilog Macros
Macro Example One
Macro Example Two
Include Files
Behavioral Verilog Comments
One-Line Comments
Multiple-Line Block Comments
Generate Statements
Structures Created Using Generate Statements
Supported Generate Statements
Generate Loop Statements
Generate Loop Statement 8-Bit Adder Example
Generate Conditional Statements
Generate Conditional Statement Coding Example
Generate Case Statements
Behavioral Verilog Generate Case Statements Coding Example
SystemVerilog Support
Introduction
Targeting SystemVerilog for a Specific File
Tcl Command to Set Properties
Compilation Units
Data Types
Declaration
Integer Data Types
Real Numbers
Void Data Type
User-Defined Types
Enum Types
Constants
Type Operator
Casting
Aggregate Data Types
Structures
Unions
Packed and Unpacked Arrays
Processes
Always Procedures
Block Statements
Procedural Timing Controls
Operators
Signed Expressions
Procedural Programming Assignments
Conditional if-else Statement
Case Statement
Loop Statements
Tasks and Functions
Tasks
Functions (Automatic and Static)
Modules and Hierarchy
Connecting Modules
Connecting Modules with Wildcard Ports
Interfaces
Modports
Miscellaneous Interface Features
Packages
SystemVerilog Constructs
Mixed Language Support
Introduction
Mixing VHDL and Verilog
Instantiation
Instantiating VHDL in Verilog
Instantiating Verilog in VHDL
Instantiation Limitations
VHDL in Verilog
Acceptable Example
Unacceptable Example
Verilog in VHDL
VHDL and Verilog Libraries
VHDL and Verilog Boundary Rules
Binding
Generics Support
Port Mapping
Port Mapping for VHDL Instantiated in Verilog
Port Mapping for Verilog Instantiated in VHDL
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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