There are 4 clocks, 4 SRs, and 16 CEs for each CLB as shown in the following figure.
Q1 and Q2 flip-flops use the same clock enables. This is different than with previous architectures because clock enables were interleaved between Q1 and Q2 flip-flops. Clock and SR are on an 8-bit LUT granularity. In other words, 8 LUTs associated with the same carry chain share a common clock and SR. SRLs use the same clock as the flip-flops associated with that LUT.
SRLs use the same write enable signal (WE) as is used for LUTRAM, which is a slice-level granularity enable signal. SR signals are optionally ignorable on a per slice level.
CE does not have any gating features, as the granularity for CE is already on a per 4 flop basis and a constant 1 can be provided for free in the interconnect control multiplexers feeding the flip-flop CE pins.
For LUTRAM mode, a separate per slice (8 LUTs) write enable is provided; one for the left half of the CLB and one for the other half. The write enable is a separate signal than the clock enable for the flops. The LUTRAM write clock is the same as the clock that drives flops in the same slice. Asynchronous FIFOs can still be constructed using LUTRAM but outputs would have to be registered in a different slice in order for read and write clocks to be different.
LUTRAM and SRL always use the same clock as CLB flip-flops, as a result the CLB flip-flops cannot be in latch mode in the same slice that uses LUTRAM or SRL. The CLE IMUX registers and flip-flops also share the same clock in a slice. Therefore, the latch mode for CLE flip-flop is not compatible with any IMUX register usage (hold-fix and pipeline mode).