HSDP support can be added to a board by adding a USB-C connector and connecting
up the high speed lines to Versal ACAP dedicated HSDP GT ports, as shown in the
following figure. By making use of the custom protocol support allowed by the USB-C/USB
3.0 specification, a board can readily have basic HSDP support with just the addition of
the HSDP connector. However, because it is necessary to first initialize a Versal ACAP
with an initial image, a target must have the JTAG interface connected to the SmartLynq+
Module. When performing the initial bring up of a Versal ACAP it is also helpful to make
use of a UART to gain further observability of the system. For this reason it is very
useful to integrate all these debug capabilities through a single connector. As a result
the HSDP debug connector has a superset option that fully enables you to gain essential
observability with a minimum connector footprint with an added benefit of scalable debug
support.
Figure 1. SmartLynq+ to HSDP on a Target Board
The following table and figures show two options for the HSDP interface. Note
that each option has tradeoffs that must be considered by the end user. For the greatest
observability use option 1. For reduced observability use option 2. The table provides a
quick summary with the pros/cons of the various options.
Option | Description | Pro | Con |
---|---|---|---|
1 | HSDP with FTDI JTAG | One connector integrates all essential debug observability | Extra cost incurred by by FTDI and related support parts/power |
2 | HSDP with PC4 JTAG | Lower cost and reduced real estate | No integrated UART support |
Figure 2. Option 1: HSDP with FTDI JTAG
Figure 3. Option 2: HSDP with PC4 JTAG
HSDP Connector
The HSDP target implements a UFP (upstream facing port) peripheral interface
through a USB-C receptacle connector. The receptacle features four power and four
ground pins, two differential pairs for high-speed USB data (though they are
connected together on devices), four shielded differential pairs for Enhanced
SuperSpeed data (two transmit and two receive pairs), two Sideband Use (SBU) pins,
and two Configuration Channel (CC) pins.
Figure 4. HSDP Connector
Note: The SmartLynq+ Module high-speed serial interface does not support
USB-C compliant devices; however, USB-C compliant devices will not be damaged if
they are accidentally plugged into this interface.
Pin assignments are identified in the following table.
Pin | USB Name | HSDP Name | Description | Pin | USB Name | HSDP Name | Description |
---|---|---|---|---|---|---|---|
A1 | GND | GND | Ground return | B12 | GND | GND | Ground return |
A2 | SSTXp1 | HSDP-TXp | HSDP diff pair, TX, positive | B11 | SSRXp1 | HSDP-RXp | HSDP diff pair, RX |
A3 | SSTXn1 | HSDP-TXn | HSDP diff pair, TX, negative | B10 | SSRXn1 | HSDP-RXn | HSDP diff pair, RX |
A4 | Vbus | Vbus | Bus power (from host) | B9 | Vbus | Vbus | Bus power (from host) |
A5 | CC1 | CC1 | Configuration channel | B8 | SBU2 | SBU2 | Sideband use (SBU) |
A6 | Dp1 | Dp1 | USB 2.0 differential pair, position 1, positive | B7 | Dn2 | Dn2 | USB 2.0 differential pair |
A7 | Dn1 | Dn1 | USB 2.0 differential pair, position 1, negative | B6 | Dp2 | Dp2 | USB 2.0 differential pair |
A8 | SBU1 | SBU1 | Sideband use (SBU) | B5 | CC2 | CC2 | Configuration channel |
A9 | Vbus | Vbus | Bus power (from host) | B4 | Vbus | Vbus | Bus power (from host). Note: This power is supplied from the SmartLynq + Module when the target is detected. The power is used to enable powering the FTDI part. Note that only minimal USB2.0 power is supplied. |
A10 | SSTXn2 | - | No connection | B3 | SSRXn2 | - | No connection |
A11 | SSTXp2 | - | No connection | B2 | SSRXn2 | - | No connection |
A12 | GND | GND | Ground return | B1 | GND | - | Ground return |
High Speed Differential Pairs
The SmartLynq+ HSDP interface supports standard USB 3.0 cables. As such, high-speed
differential pairs (HSDP-TXp/HSDP-TXn and HSDP-RXp/HSDP-RXn) must comply with the
electrical requirements specified in Section 5.6.1 of the Universal Serial Bus
3.0 Specification. The key electrical requirements are identified in the
following table.
Parameter | Value |
---|---|
Characteristic impedance | 90Ω ± 7Ω |
Intra-pair (P-to-N) skew | Less than 15 pS per meter |
Differential insertion loss | 30 AWG: 1.4 dB/m @ 625 MHz, 2.0 dB/m @ 1.25 GHz, 3.00 dB/m @ 2.50 GHz |
28 AWG: 1.2 dB/m @ 625 MHz, 1.8 dB/m @ 1.25 GHz, 2.65 dB/m @ 2.50 GHz |
Configuration Channel (CC) Connections
The CC lines are used to determine orientation and power sense. HSDP targets do NOT
use the power from the host, therefore the power sense is ignored. This is how the
cable orientation is detected from the host:
- If CC1 is pulled down, the cable is not flipped.
- If CC2 is pulled down, the cable is flipped.
The CC connections are shown in the following figure.
Figure 5. CC Connections
The CC lines should be connected as follows in order to have the host detect
the device as a USB 2.0 peripheral. The SmartLynq+ Module supports USB-C in a single
orientation currently for HSDP capability. The following LED status can be used to
check if the USB-C cable is connected in the expected orientation:
- Green: USB-C is properly connected
- Amber: Either the cable is not connected or needs to be flipped
- Pressing the "SL+" tab select key on the display shows the root cause for the amber LED.
HSDP Name | Connection | Desciption |
---|---|---|
CC1 | Rd = 5.1 KΩ | The UFP Rd value is fixed at 5.1 kΩ. |
CC2 | Rd = 5.1 KΩ | The UFP Rd value is fixed at 5.1 kΩ. |
Versal ACAP Connectivity
- See the VCK190 Schematics (XTP610) for a sample board connectivity.
- For the HSDP connector, follow the recommended USBC guidelines to run at 10 Gb/s. The preceding table contains some of the highlights of these requirements.
- When connecting the GTs from the Versal ACAP to the HSDP connector, keep the differential lengths matched and close to the connector.
- For more information on adding HSDP to Versal ACAP designs, seethe Versal ACAP Design Guide (UG1273).