LPD_SLCR Module Description
| Module Name | LPD_SLCR Module |
|---|---|
| Modules of this Type | LPD_SLCR |
| Base Address | 0x00FF410000 (LPD_SLCR) |
| Description | LPD System-level Control Registers |
LPD_SLCR Module Register Summary
| Register Name | Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| WProt | 0x0000000000 | 1 | rwNormal read/write | 0x00000000 | LP Domain SLCR Write protection register |
| APB_CTRL | 0x0000000004 | 1 | rwNormal read/write | 0x00000000 | APB Programming Interface Control |
| ISR | 0x0000000008 | 1 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register. Sticky register, holds the value of interrupts until cleared by writing a 1 to the corresponding bit. Each bit is described in Bit Field Details. |
| APB_IMR | 0x000000000C | 1 | roRead-only | 0x00000001 | Interrupt Mask Register. Read-only. Contents can be altered by writing corresponding bit in the IDR or the IER registers. |
| APB_IER | 0x0000000010 | 1 | woWrite-only | 0x00000000 | Interrupt Enable Register. Writing a 1 to a bit in this register will unmask the corresponding interrupt in the Interrupt Mask Register (IMR[bit] -> 0) |
| APB_IDR | 0x0000000014 | 1 | woWrite-only | 0x00000000 | Interrupt Disable Register. Writing a 1 to a bit in this register will mask the corresponding interrupt, as reflected in the Interrupt Mask Register (IMR[bit] -> 1) |
| SAFETY_CHK0 | 0x0000000060 | 32 | rwNormal read/write | 0x00000000 | Safety Check register |
| SAFETY_CHK1 | 0x0000000064 | 32 | rwNormal read/write | 0x00000000 | Safety Check register |
| SAFETY_CHK2 | 0x0000000068 | 32 | rwNormal read/write | 0x00000000 | Safety Check register |
| SAFETY_CHK3 | 0x000000006C | 32 | rwNormal read/write | 0x00000000 | Safety Check register |
| LPD_DMA_SMID_CFG | 0x0000000074 | 32 | rwNormal read/write | 0x00000000 | System Master ID Context Configuration for LPD DMA. Selects between 1 of 2 contexts for each DMA channel. |
| RPU0_SMID_CFG | 0x000000007C | 32 | rwNormal read/write | 0x00000000 | Context Configuration for RPU0 |
| RPU1_SMID_CFG | 0x0000000080 | 32 | rwNormal read/write | 0x00000000 | Context Configuration for RPU1 |
| HSDP_CFG | 0x0000000088 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | HSDP Configuration |
| XRAM_STATUS | 0x000000008C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | XRAM Available Status |
| LPD_AXI_PL_Width | 0x0000009000 | 16 | mixedMixed types. See bit-field details. | 0x00000200 | LPD_AXI_PL Interface to PL |
| CCI_CFG_0 | 0x000000A000 | 32 | mixedMixed types. See bit-field details. | 0x00030FC0 | Config of QoS, Snoop channel, DVM msg |
| CCI_CFG_1 | 0x000000A004 | 32 | mixedMixed types. See bit-field details. | 0x000003C0 | Ordering and dependency settings |
| CCI_MAP | 0x000000A008 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | CCI Port Striping Control |
| SMMU | 0x000000A020 | 32 | mixedMixed types. See bit-field details. | 0x0000007F | Tie off signals for SMMU |
| APU | 0x000000A040 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | APU Configuration |