The common features of the PC-CFR core and individual configuration features of both implementations of PC-CFR (using PL resources only and using DFE-CFR + PL resources) are as follows:
• Support for multiple air interface standards.
• Smart Peak Processing mode for supporting wide transmit bandwidth up to 400 MHz, processes incoming samples at >1.2 times instantaneous bandwidth (iBW) reducing resource utilization.
• Support for power and frequency dynamics.
For additional features see Features (cont.) .
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
AMD Zynq™ UltraScale+™ RFSoC DFE
AMD UltraScale™ Architecture
7 series FPGAs |
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Supported User Interfaces |
AXI4-Stream, AXI4-Lite |
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Provided with Core |
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Design Files |
Encrypted RTL |
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Example Design |
Not Provided |
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Test Bench |
VHDL |
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Constraints File |
Vivado XDC |
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Simulation Model |
VHDL and Verilog Structural Simulation Model MATLAB® Model available |
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Supported
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CFR Reference Design available at www.xilinx.com/products/intellectual-property/ef-di-pc-cfr.html |
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Tested Design Flows (2) |
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Design Entry |
AMD Vivado™ Design Suite |
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Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing . |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54486 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP catalog. 2. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing . |
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