This register captures different status conditions of the core.
Table 2-9:
Status Register (0x2C)
|
Bits
|
Name
|
Reset Value
|
Access
|
Description
|
|
31:13
|
Reserved
|
NA
|
NA
|
Reserved
|
|
12
|
Current command type under processing
|
0
|
R
|
0 - Short command when bit 11 is 1
1- long command when bit 11 is 1
|
|
11
|
Command execution in progress
|
0
|
R
|
Status of command execution in command mode.
When 0: No commands are being processed. Can shift to Video mode.
|
|
10
|
Waiting for data
|
0
|
R
|
Waiting for data to process long command. There is no timeout for this state in the core and it keeps waiting forever and until the data is received or data FIFO is reset.
|
|
9
|
Data FIFO Empty
|
0
|
R
|
Data FIFO Empty condition.
Note:
Reset Value is 1 when Command mode is enabled.
|
|
8
|
Data FIFO Full
|
0
|
R
|
Data FIFO Full condition
|
|
7
|
Ready for packet
|
0
|
R
|
1: The core is ready to accept a long command. If this bit is 0, any long command written to the command register is ignored
|
|
6
|
Ready for short packet
|
0
|
R
|
1: The core is ready to accept a short command. If this bit is 0, any command written to the command register is ignored
|
|
5:0
|
Command Queue Vacancy
|
0x20
|
R
|
This number gives an estimate of number of command queue entries that can safely be written to the Queue before it gets Full.
Command FIFO Depth is 31.
Command FIFO will be Full when this count is 1.
Number of further commands you can write = Vacancy count - 1
|