Register Space - 2.2 English

PG238 MIPI DSI Transmitter Subsystem Product Guide

Document ID
PG238
Release Date
2022-04-26
Version
2.2 English

This section details registers available in the MIPI DSI TX Subsystem. The address map is split into following regions:

MIPI DSI TX Controller core

MIPI D-PHY core

Each IP core is given an address space of 64K. Example offset addresses from the system base address when the MIPI D-PHY registers are enabled are shown in Table: Sub-Core Address Offsets . Registers are provided for informational and debug purposes. For more details, refer provided driver API for the supported control of the MIPI DSI TX Subsystem.

Table 2-2: Sub-Core Address Offsets

IP Cores

Offset

MIPI DSI TX Controller

0x0_0000

MIPI D-PHY

0x1_0000