Captures different error/status information of the core.
Bits |
Name |
Reset Value |
Access |
Description |
---|---|---|---|---|
31:3 |
Reserved |
NA |
NA |
Reserved |
2 |
Command Queue FIFO Full |
0x0 |
R/W1C (1) |
Asserted when command queue FIFO full condition detected. |
1 |
Unsupported/Reserved Data type |
0x0 |
R/W1C (1) |
Asserted when unsupported/reserved data types seen in command queue. |
0 |
Pixel Data underrun |
0x0 |
R/W1C (1) |
Byte stream FIFO starves for Pixel during HACT transmission. (2) |
Notes: 1. W1C – Write 1 to Clear (to clear register bit, you have to write 1 to corresponding bits). 2. Pixel Data underrun is not expected during normal core operation, which implies that the rate of incoming data is insufficient to keep up with the outgoing data rate. |