MIPI DSI TX Controller

The MIPI DSI TX Controller core consists of multiple layers defined in the MIPI DSI TX 1.3 specification, such as the lane management layer, low level protocol, and pixel-to-byte conversion.

The DSI TX Controller core receives stream of image data through an input stream interface. Based on the targeted display peripheral supported resolution and timing requirements, the controller must be programmed with required timing values. The controller then generates packets fulfilling the required video timing markers based on different video transmit mode sequences. In addition, the core supports sending short command packets during BLLP periods of video frames and also supports to send long or short command packets when configured in command mode. Sub-block details of MIPI DSI TX Controller are shown in This Figure .

Figure 1-2: Sub-blocks
X-Ref Target - Figure 1-2

The features of this core include:

• 1 to 4 Lane support with a data rate of 2500 Mb/s per lane, for UltraScale+ only: Allows more bandwidth than that provided by one lane. If you are trying to avoid high clock rates, the subsystem can expand the data path to multiple lanes and obtain approximately linear increases in peak bus bandwidth.

• Generates PPI transfers towards DPHY with continuous clock.

• ECC and CRC calculation based on algorithm specified in DSI Specification: The correct interpretation of the data identifier and word count values is vital to the packet structure. ECC is calculated over packet header.

To detect possible errors in transmission, a checksum is calculated over each data packet. The checksum is realized as 16-bit CRC. The generator polynomial is x16+x12+x5+x0.

The CRC is computed only for the pixel bytes. The CRC fields for all other long packets are filled with 0x0000.

• Command Queue, data queue and command generation logic for non-video packets: To send non-video packets to display peripheral, a command queue is implemented to store the required command packets to be sent (Ex: Color mode on-off, Shutdown peripheral command, etc). When in video mode, the controller finds enough time-slot available during the video blanking periods, these short commands are sent over DSI link. When in command mode, the controller sends only the commands long/short programmed through register. Video data is not sent in this mode.

• All three video modes supported (Non-burst with sync pulses, Non-burst with sync events, Burst mode)

• Pixel to byte Conversion: The input video stream is expected to be compliant with AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] recommendations. Based on data type the incoming pixel stream is converted to byte stream to match with the DSI requirements detailed in sec 8.8 of the MIPI Alliance Standard for DSI specification [Ref 1] .

RGB component ordering, packed, unpacked mechanisms differ between AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] and DSI Specification. Refer to AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] and DSI specifications for better understanding on component ordering, packed, unpacked styles, etc.

This Figure through This Figure illustrate the incoming pixel stream ordering on an AXI4-Stream video interface for different data types and pixels per clock combinations.

Figure 1-3: Single Pixel RGB888
X-Ref Target - Figure 1-3

Figure 1-4: Dual Pixels RGB888
X-Ref Target - Figure 1-4

Figure 1-5: Quad Pixels RGB888
X-Ref Target - Figure 1-5

Figure 1-6: Single Pixel RGB666 (Loosely, Packed)
X-Ref Target - Figure 1-6

Figure 1-7: Dual Pixels RGB666 (Loosely, Packed)
X-Ref Target - Figure 1-7

Figure 1-8: Quad Pixels RGB666 (Loosely, Packed)
X-Ref Target - Figure 1-8

Figure 1-9: Single Pixel RGB565
X-Ref Target - Figure 1-9

Figure 1-10: Dual Pixels RGB565
X-Ref Target - Figure 1-10

Figure 1-11: Quad Pixels RGB565
X-Ref Target - Figure 1-11

Figure 1-12: Single Pixel Compressed
X-Ref Target - Figure 1-12

Figure 1-13: Dual Pixel Compressed
X-Ref Target - Figure 1-13

Figure 1-14: Quad Pixel Compressed
X-Ref Target - Figure 1-14

• Register programmable EoTp generation support.

• Interrupt generation to indicate detection of under run condition during pixel transfer and unsupported data types detected in command queue.

• One horizontal scanline of active pixels are transferred as one single DSI packet.

• All mandatory uncompressed pixel formats 16 bpp (RGB565), 18 bpp (RGB666 packed), 18 bpp (RGB666 loosely packed), 24 bpp (RGB888) are supported.

• Core accepts compressed data type from GUI selection, where the user is expected to pump in the compressed data. Core passes those stream of data without any conversion.

MIPI DSI TX Controller - 2.2 English

PG238 MIPI DSI Transmitter Subsystem Product Guide