AXI Bridge Subsystem - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
Release Date
1.0 English
  • AXI4-MM access to PCIe address space
  • PCIe access to AXI4-MM address space
  • Tracks and manages Transaction Layer Packets (TLPs) completion processing
  • Detects and indicates error conditions with interrupts
  • Supports up to six PCIe 32-bit or three 64-bit PCIe BARs as endpoint (EP)
  • Supports up to two PCIe 32-bit or a single PCIe 64-bit BAR as root port (RP)