One or more PCIe BAR of any physical function (PF) or virtual function
(VF) can be mapped to the AXI4-Lite master interface.
This selection must be done at the point of configuring the IP. The function ID, BAR ID
(BAR hit), VF group, and VF group offset will be made available as part of
awuser of the
AXI4-Lite interface to help the user logic
identify the source of memory access.
bits mapping is listed in AXI4-Lite Master Ports.
Virtual function group (VFG) refers to the VF group number. It is equivalent to the PF number associated with the corresponding VF. VFG_OFFSET refer to the VF number with respect to a particular PF. Note that this is not the FIRST_VF_OFFSET of each PF.
For example, if both PF0 and PF1 has 8 VFs, and FIRST_VF_OFFSET for PF0 and PF1 is 4 and 11 and below is the mapping for VFG and VFG_OFFSET.
|Function Number||PF Number||VFG||VFG_OFFSET|
|4||0||0||0 (Because FIRST_VF_OFFSET for PF0 is 4, the first VF of PF0 starts at FN_NUM=4 and VFG_OSSET=0 indicates this is the first VF for PF0)|
|5||0||0||1 (VFG_OSSET=1 indicates this is the second VF for PF0)|
|12||1||1||0 (VFG=1 indicates this VF is associated with PF1)|
Each host initiated access can be uniquely mapped to the 64 bit AXI address space through the PCIe to AXI BAR translation.
Because all functions shares the same AXI4 master address space, a mechanism is needed to map requests from different functions to a distinct address space on the AXI master side. This below shows how PCIe to AXI translation vector is used. Note that all VFs belonging to the same PF shares the same PCIe to AXI translation vector. Therefore, the AXI address space of each VF is concatenated together. Use VFG_OFFSET to calculate the actual starting address of AXI for a particular VF.
To summarize, m_axil_awaddr is determined as:
- For PF,
- For VF,
pcie2axi_vec+ (VFG_OFFSET + 1)*
pcie2axi_vec is PCIe to AXI BAR
translation (that can be set during IP configuration.).
axib_offset is the address offset in
the requested target space.
Each host initiated access can be uniquely mapped to the 64 bit AXI address space. One outstanding read and one outstanding write are supported on this interface.
Expansion ROM BAR can also be mapped to AXI4-Lite interface at the IP configuration time.