AXI4-Lite Master Ports - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. Config AXI4-Lite Memory Mapped Write Master Interface Port Descriptions
Signal Name I/O Description
m_axil_awaddr[31:0] O This signal is the address for a memory mapped write to the user logic from the host.
m_axil_awprot[2:0] O Protection type.
m_axil_awvalid O The assertion of this signal means there is a valid write request to the address on m_axil_awaddr.
m_axil_awready I Master write address ready.

m_acil_awuser [29:0]

 O

m_axib_awuser[7:0] = function number

m_axib_awuser[15:8] = reserved

m_axib_awuser[18:16] = bar id

m_axib_awuser[26:19] = vf offset

m_axib_awuser[28:27] = vf id
m_axil_wdata[31:0] O Master write data.
m_axil_wstrb[3:0] O Master write strobe.
m_axil_wvalid O Master write valid.
m_axil_wready I Master write ready.
m_axil_bvalid I Master response valid.
m_axil_bresp[1:0] I  
m_axil_bready O Master response valid.

Table 2. Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions
Signal Name I/O Description
m_axil_araddr[31:0] O This signal is the address for a memory mapped read to the user logic from the host.

m_axil_aruser[28:0]

 O

m_axib_aruser[7:0] = function number

m_axib_aruser[15:8] = reserved

m_axib_aruser[18:16] = bar id

m_axib_aruser[26:19] = vf offset

m_axib_aruser[28:27] = vf id
m_axil_arprot[2:0] O Protection type.
m_axil_arvalid O The assertion of this signal means there is a valid read request to the address on m_axil_araddr.
m_axil_arready I Master read address ready.
m_axil_rdata[31:0] I Master read data.
m_axil_rresp[1:0] I Master read response.
m_axil_rvalid I Master read valid.
m_axil_rready O Master read ready.