AXI4-Lite Slave CSR Ports - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID: PG344
Release Date: 2022-05-20
Version: 1.0 English

Table 1. Config AXI4-Lite Memory Mapped Write Slave CSR Interface Signals
Signal Name	I/O	Description
s_axil_csr_awaddr[31:0]	I	This signal is the address for a memory mapped write to the DMA from the user logic. s_axil_csr_awaddr[15]: 1'b1 – QDMA CSR register 1'b0 – Bridge register
s_axil_csr_awvalid	I	The assertion of this signal means there is a valid write request to the address on s_axil_csr_awaddr.
s_axil_csr_awprot[2:0]	I	Protection type. This port is not being used.
s_axil_csr_awready	O	Slave write address ready.
s_axil_csr_wdata[31:0]	I	Slave write data.
s_axil_csr_wstrb[3:0]	I	Slave write strobe.
s_axil_csr_wvalid	I	Slave write valid.
s_axil_csr_wready	O	Slave write ready.
s_axil_csr_bvalid	O	Slave write response valid.
s_axil_csr_bresp[1:0]	O	Slave write response.
s_axil_csr_bready	I	Save response ready.

Table 2. Config AXI4-Lite Memory Mapped Read Slave CSR Interface Signals
Signal Name	I/O	Description
s_axil_csr_araddr[31:0]	I	This signal is the address for a memory mapped read to the DMA from the user logic. s_axil_csr_araddr[15]: 1'b1 – QDMA register 1'b0 – Bridge register
s_axil_csr_arprot[2:0]	I	Protection type. This port is not being used.
s_axil_csr_arvalid	I	The assertion of this signal means there is a valid read request to the address on s_axil_csr_araddr.
s_axil_csr_arready	O	Slave read address ready.
s_axil_csr_rdata[31:0]	O	Slave read data.
s_axil_csr_rresp[1:0]	O	Slave read response.
s_axil_csr_rvalid	O	Slave read valid.
s_axil_csr_rready	I	Slave read ready.