AXI4 Memory Mapped DMA Ports - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. AXI4 Memory Mapped DMA Read Address Interface Signals
Signal Name Direction Description
m_axi_araddr

[C_M_AXI_ADDR_WIDTH-1:0]

O This signal is the address for a memory mapped read to the user logic from the DMA.
m_axi_arid [3:0] O Standard AXI4 description, which is found in the AXI4 Protocol Specification AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A).
m_axi_aruser[31:0] O

m_axi_aruser[18:0] = reserved

m_axi_aruser[31:19] = queue number

m_axi_arlen[7:0] O Master read burst length.
m_axi_arsize[2:0] O Master read burst size.
m_axi_arprot[2:0] O Protection type.
m_axi_arvalid O The assertion of this signal means there is a valid read request to the address on m_axi_araddr.
m_axi_arready I Master read address ready.
m_axi_arlock O Lock type.
m_axi_arcache[3:0] O Memory type.
m_axi_arburst[1:0] O Master read burst type.

Table 2. AXI4 Memory Mapped DMA Read Interface Signals
Signal Name Direction Description
m_axi_rdata

[C_M_AXI_DATA_WIDTH-1:0]

I Master read data.
m_axi_rid [3:0] I Master read ID.
m_axi_rresp[1:0] I Master read response.
m_axi_rlast I Master read last.
m_axi_rvalid I Master read valid.
m_axi_rready O Master read ready.
m_axi_ruser

[C_M_AXI_DATA_WIDTH/8-1:0]

I Master read odd data parity, per byte. This port is enabled only in Data Protection mode.
Table 3. AXI4 Memory Mapped DMA Write Address Interface Signals
Signal Name Direction Description
m_axi_awaddr

[C_M_AXI_ADDR_WIDTH-1:0]

O This signal is the address for a memory mapped write to the user logic from the DMA.

m_axi_awid[3:0]

O Master write address ID.
m_axi_awuser[31:0] O

m_axi_awuser[18:0] = reserved

m_axi_awuser[31:19] = queue number

m_axi_awlen[7:0] O Master write address length.
m_axi_awsize[2:0] O Master write address size.
m_axi_awburst[1:0] O Master write address burst type.
m_axi_awprot[2:0] O Protection type.
m_axi_awvalid O The assertion of this signal means there is a valid write request to the address on m_axi_araddr.
m_axi_awready I Master write address ready.
m_axi_awlock O Lock type.
m_axi_awcache[3:0] O Memory type.
Table 4. AXI4 Memory Mapped DMA Write Interface Signals
Signal Name Direction Description
m_axi_wdata

[C_M_AXI_DATA_WIDTH-1:0]

O Master write data.
m_axi_wlast O Master write last.
m_axi_wstrb[31:0] O Master write strobe.
m_axi_wvalid O Master write valid.
m_axi_wready I Master write ready.
m_axi_wuser

[C_M_AXI_DATA_WIDTH/8-1:0]

O Master write user.

m_axi_wuser[C_M_AXI_DATA_WIDTH/8-1:0] = write data odd parity, per byte. This port is enabled only in Data Protection mode.

Table 5. AXI4 Memory Mapped DMA Write Response Interface Signals
Signal Name Direction Description
m_axi_bvalid I Master write response valid.
m_axi_bresp[1:0] I Master write response.

m_axi_bid[3:0]

I Master response ID.
m_axi_bready O Master response ready.