AXI4 Memory Mapped Master Bypass Write Address Interface Signals - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. AXI4 Memory Mapped Master Bypass Write Address Interface Signals
Signal Name Direction Description
m_axib_awaddr

[AXI_ADR_WIDTH-1:0]

O This signal is the address for a memory mapped write to the user logic from the host.
m_axib_awid

[ID_WIDTH-1:0]

O Master write address ID.
m_axib_awlen[7:0] O Master write address length.
m_axib_awsize[2:0] O Master write address size.
m_axib_awburst[1:0] O Master write address burst type.
m_axib_awprot[2:0] O 3’h0
m_axib_awvalid O The assertion of this signal means there is a valid write request to the address on m_axib_araddr.
m_axib_awready I Master write address ready.
m_axib_awlock O 1’b0
m_axib_awcache[3:0] O 4’h0