AXI4 Memory Mapped Master Bypass Write Interface Signals - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. AXI4 Memory Mapped Master Bypass Write Interface Signals
Signal Name Direction Description
m_axib_wdata

[DATA_WIDTH-1:0]

 O Master write data.
m_axib_wlast O Master write last.
m_axib_wstrb O Master write strobe.
m_axib_wvalid O Master write valid.
m_axib_wready I Master write ready.
m_axib_wuser

[DATA_WIDTH/8-1:0]

 O Parity ports for read interface. This port is enabled only in Propagate Parity mode.