AXI4 Memory Mapped Master Bypass Write Response Interface Signals - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. AXI4 Memory Mapped Master Bypass Write Response Interface Signals
Signal Name Direction Description
m_axib_bvalid I Master write response valid.
m_axib_bresp[1:0] I Master write response.
m_axib_bid

[ID_WIDTH-1:0]

 I Master write response ID.
m_axib_bready O Master response ready.