The following table describes the tests provided for simulation. These tests are selected based on the QDMA IP configuration. For example, if the AXI4-MM only option is selected, the qdma_mm_test0 test case is selected and will be executed during simulation.
The test bench compares the write data with the read data for correctness.
|AXI4-MM and AXI4-ST with completion||qdma_mm_st_test0||Verilog||
This test is a combination of test cases qdma_mm_test0 and qdma_st_test0.