Figure 1. Basic Tab for DMA Functional Mode
The options are defined as follows:
- Functional Mode
- Set to DMA Subsystem.
- Allows you to select the Basic or Advanced mode of the configuration of subsystem.
- Device /Port Type
- Only PCI Express® Endpoint device mode is supported.
- PCIe Block Location
- Selects from the available integrated blocks to enable generation of location-specific constraint files and pinouts. This selection is used in the default example design scripts. This option is not available if a Xilinx Development Board is selected.
- Lane Width
- The subsystem requires the selection of the initial lane width. For supported lane widths and link speeds, see the Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device.
- Maximum Link Speed
- The subsystem requires the selection of the PCIe Gen speed.
- Reference Clock Frequency
- The default is 100 MHz, but 125 MHz and 250 MHz are also supported.
- AXI Address Width
- Currently, only 64-bit width is supported.
- AXI Data Width
- Select 64, 128, 256-bit, or 512-bit. The subsystem allows you to select the Interface Width, as defined in the Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).
- AXI Clock Frequency
- Select 62.5 MHz, 125 MHz or 250 MHz depending on the lane width/speed.
- DMA Interface Option
- Select AXI4 Memory Mapped and AXI4-Stream.
- AXI4-Lite Slave Interface
- Select to enable the AXI4-Lite slave Interface.
- Enable PIPE Simulation
- When selected, this option enables an external third-party bus functional model (BFM) to connect to the PIPE interface of the integrated block for PCIe.
Recommended: Xilinx recommends that you select the correct GT starting quad before setting the link rate and width. Selecting line rate and width prior to selecting GT quad can have adverse effects.