The C2H channel handles DMA transfers from the card to the host. The
instantiated number of C2H channels is controlled in the
IDE. Similarly the number of outstanding transfers is configured
WNUM_RIDS, which is the number of C2H
channel request IDs. In an AXI4-Stream configuration,
the details of the DMA transfer are set up in advance of receiving data on the AXI4-Stream interface. This is normally accomplished
through receiving a DMA descriptor. After the request ID has been prepared and the
channel is enabled, the AXI4-Stream interface of the
channel can receive data and perform the DMA to the host. In an AXI4 MM interface configuration, the request IDs are allocated as the
read requests to the AXI4 MM interface are issued.
Similar to the H2C channel, a given request ID is outstanding until the write request
has been completed. In the case of the C2H channel, write request completion is when the
write request has been issued as indicated by the PCIe IP.
When multiple channels are enabled, transactions on the AXI4 Master interface are interleaved between all selected channels. Simple round robin protocol is used to service all channels. Transactions granularity depends on host MaxPayload Size (MPS), page size, and other host settings.