C2H Channel Completed Descriptor Count (0x48) - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2022-05-20
Version
1.0 English
Table 1. C2H Channel Completed Descriptor Count (0x48)
Bit Index Default Access Type Description
31:0 32’h0 RO

compl_descriptor_count

The number of competed descriptors update by the engine after completing each descriptor in the list.

Reset to 0 on rising edge of Control register, run bit (C2H Channel Control (0x04)).