Clocking - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2022-05-20
Version
1.0 English

The programmable logic integrated block for PCIe (PL PCIE) requires a 100, 125, or 250 MHz reference clock input. The following figure shows the clocking architecture. The user_clk clock is available for use in the fabric logic. The user_clk clock can be used as the system clock.

Figure 1. USER_CLK Clocking Architecture

All user interface signals are timed with respect to the same clock (user_clk) which can have a frequency of 62.5, 125, or 250 MHz depending on the configured link speed and width.

Each link partner device shares the same reference clock source. The following figures show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI ExpressĀ® root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should be used.

Note: The following figures are high-level representations of the board layout. Ensure that coupling, termination, and details are correct when laying out a board.
Figure 2. Embedded System Using 100 MHz Reference Clock
Figure 3. Open System Add-In Card Using 100 MHz Reference Clock