programmable logic integrated block for
PCIe (PL PCIE) requires a 100, 125, or 250 MHz reference clock input. The following
figure shows the clocking architecture. The
user_clk clock is available for use in the fabric
user_clk clock can be used as the system
All user interface signals are timed with respect to the same clock (
user_clk) which can have a frequency of 62.5, 125, or 250 MHz
depending on the configured link speed and width.
Each link partner device shares the same reference clock source. The following figures show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI Express® root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should be used.