Descriptor Bypass Mode

Descriptor Bypass Mode - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2022-05-20

Version

1.0 English

In the PCIe DMA tab of the Vivado IDE, if Descriptor Bypass for Read (H2C) or Descriptor Bypass for Write (C2H) is selected, these ports are present. Each binary bit corresponds to a channel (LSB correspond to Channel 0). Value 1 in bit positions means the corresponding channel descriptor bypass is enabled.

Table 1. H2C 0-3 Descriptor Bypass Port
Port	Direction	Description
h2c_dsc_byp_ready	O	Channel is ready to accept new descriptors. After h2c_dsc_byp_ready is deasserted, one additional descriptor can be written. The Control register 'Run' bit must be asserted before the channel accepts descriptors.
h2c_dsc_byp_load	I	Write the descriptor presented at h2c_dsc_byp_data into the channel’s descriptor buffer.
h2c_dsc_byp_src_addr[63:0]	I	Descriptor source address to be loaded.
h2c_dsc_byp_dst_addr[63:0]	I	Descriptor destination address to be loaded.
h2c_dsc_byp_len[27:0]	I	Descriptor length to be loaded.
h2c_dsc_byp_ctl[15:0]	I	Descriptor control to be loaded. [0]: Stop. Set to 1 to stop fetching next descriptor. [1]: Completed. Set to 1 to interrupt after the engine has completed this descriptor. [3:2]: Reserved. [4]: EOP. End of Packet for AXI-Stream interface. [15:5]: Reserved. All reserved bits can be forced to 0s. control port "h2c_dsc_byp_ctl[4:0]" are same as in descriptor control, refer to Table 6.

Table 2. C2H 0-3 Descriptor Bypass Ports
Port	Direction	Description
c2h_dsc_byp_ready	O	Channel is ready to accept new descriptors. After c2h_dsc_byp_ready is deasserted, one additional descriptor can be written. The Control register 'Run' bit must be asserted before the channel accepts descriptors.
c2h_dsc_byp_load	I	Descriptor presented at c2h_dsc_byp_* is valid.
c2h_dsc_byp_src_addr[63:0]	I	Descriptor source address to be loaded.
c2h_dsc_byp_dst_addr[63:0]	I	Descriptor destination address to be loaded.
c2h_dsc_byp_len[27:0]	I	Descriptor length to be loaded.
c2h_dsc_byp_ctl[15:0]	I	Descriptor control to be loaded. [0]: Stop. Set to 1 to stop fetching next descriptor. [1]: Completed. Set to 1 to interrupt after the engine has completed this descriptor. [3:2]: Reserved. [4]: EOP. End of Packet for AXI-Stream interface. [15:5]: Reserved. All reserved bits can be forced to 0s. control port "h2c_dsc_byp_ctl[4:0]" are same as in descriptor control, refer to Table 6.

The following timing diagram shows how to input the descriptor in descriptor bypass mode. When dsc_byp_ready is asserted, a new descriptor can be pushed in with the dsc_byp_load signal.

Figure 1. Timing Diagram for Descriptor Bypass Mode

Important: Immediately after dsc_byp_ready is deasserted, one more descriptor can be pushed in. In the above timing diagram, a descriptor is pushed in when dsc_byp_ready is deasserted.