The XDMA Subsystem uses a linked list of descriptors that specify the source, destination, and length of the DMA transfers. Descriptor lists are created by the driver and stored in host memory. The DMA channel is initialized by the driver with a few control registers to begin fetching the descriptor lists and executing the DMA operations.
Descriptors describe the memory transfers that the XDMA should perform. Each channel has its own
descriptor list. The start address of each channel's descriptor list is initialized in
hardware registers by the driver. After the channel is enabled, the descriptor channel
begins to fetch descriptors from the initial address. Thereafter, it fetches from the
Nxt_adr[63:0] field of the last descriptor that was
fetched. Descriptors must be aligned to a 32 byte boundary.
The size of the initial block of adjacent descriptors are specified with
the Dsc_Adj register. After the initial fetch, the descriptor channel uses the
Nxt_adj field of the last fetched descriptor to determine
the number of descriptors at the next descriptor address. A block of adjacent
descriptors must not cross a 4K address boundary. The descriptor channel fetches as many
descriptors in a single request as it can, limited by MRRS, the number the adjacent
descriptors, and the available space in the channel's descriptor buffer.
Every descriptor in the descriptor list must accurately describe the
descriptor or block of descriptors that follows. In a block of adjacent descriptors, the
Nxt_adj value decrements from the first descriptor
to the second to last descriptor which has a value of zero. Likewise, each descriptor in
the block points to the next descriptor in the block, except for the last descriptor
which might point to a new block or might terminate the list.
Termination of the descriptor list is indicated by the Stop control bit. After a descriptor with the Stop control bit is observed, no further descriptor fetches are issued for that list. The Stop control bit can only be set on the last descriptor of a block.
When using an AXI4 memory mapped interface, DMA addresses to the card are not translated. If the Host does not know the card address map, the descriptor must be assembled in the user logic and submitted to the DMA using the descriptor bypass interface.
|Offset||Field||Bit Index||Sub Field||Description|
|0x0||Magic||15:0||16'had4b. Code to verify that the driver generated descriptor is valid.|
|0x0||1:0||Reserved set to 0's|
|0x0||Nxt_adj||5:0||The number of additional adjacent descriptors after
the descriptor located at the next descriptor address field.
A block of adjacent descriptors cannot cross a 4k boundary.
|0x0||Control||5, 6, 7||Reserved|
|0x0||4||EOP||End of packet for stream interface.|
|0x0||1||Completed||Set to 1 to interrupt after the engine has completed
this descriptor. This requires global
IE_DESCRIPTOR_COMPLETED control flag set in the H2C/C2H Channel control register.
|0x0||0||Stop||Set to 1 to stop fetching descriptors for this descriptor list. The stop bit can only be set on the last descriptor of an adjacent block of descriptors.|
|0x04||Length||31:28||Reserved set to 0's|
|0x04||27:0||Length of the data in bytes.|
|0x0C-0x8||Src_adr||63:0||Source address for H2C and memory mapped transfers.
Metadata writeback address for C2H transfers.
|0x14-0x10||Dst_adr||63:0||Destination address for C2H and memory mapped transfers. Not used for H2C stream.|
|0x1C-0x18||Nxt_adr||63:0||Address of the next descriptor in the list.|
Bit_width* 512 deep FIFO to hold all descriptors in the descriptor engine. This descriptor FIFO is shared with all selected channels.
- For Gen3x16 and Gen4x8 with 4H2C and 4C2H design, AXI bit width is 512 bits. FIFO depth is 512 bit * 512 = 64 B * 512 = 32 KB (1K descriptors). This FIFO is shared by 8 DMA engines.
- For Gen3x8 with 2H2C and 2C2H design, AXI bit width is 256 bits. FIFO depth is 256 bit * 512 = 32 B * 512 = 16 KB (512 descriptors). This FIFO is shared by 4 DMA engines.