When the subsystem is configured as a Root Port, configuration traffic is generated by using the PCI Express enhanced configuration access mechanism (ECAM). ECAM functionality is available only when the core is configured as a Root Port. Reads and writes to a certain memory aperture are translated to configuration reads and writes, as specified in the PCI Express Base Specification (v3.0), §7.2.2.
The address breakdown is defined in the following table. ECAM is used in conjunction with Bridge Register Memory Map only when used in both AXI Bridge for PCIe Gen3 core as well as DMA/Bridge Subsystem for PCIe in AXI Bridge mode core. DMA/Bridge Subsystem for PCIe Register Memory Map does not have ECAM functionality.
When an ECAM access is attempted to the primary bus number, which defaults as bus 0 from reset, then access to the type 1 PCI Configuration Header of the integrated block in the Enhanced Interface for PCIe is performed. When an ECAM access is attempted to the secondary bus number, then type 0 configuration transactions are generated. When an ECAM access is attempted to a bus number that is in the range defined by the secondary bus number and subordinate bus number (not including the secondary bus number), then type 1 configuration transactions are generated. The primary, secondary, and subordinate bus numbers are written by Root Port software to the type 1 PCI Configuration Header of the Enhanced Interface for PCIe in the beginning of the enumeration procedure.
When an ECAM access is attempted to a bus number that is out of the
bus_number and subordinate bus number range, the bridge does not generate a
configuration request and signal
SLVERR response on
the AXI4-Lite bus. When the Bridge is configured
for EP (
PL_UPSTREAM_FACING = TRUE), the underlying
Integrated Block configuration space and the core memory map are available at the
beginning of the memory space. The memory space looks like a simple
configuration space. When the Bridge is
configured for RC (
PL_UPSTREAM_FACING = FALSE), the
same is true, but it also looks like an ECAM access to primary bus, Device 0,
When the subsystem is configured as a Root Port, the reads and writes of the local ECAM are Bus 0. Because the ACAP only has a single Integrated Block for PCIe core, all local ECAM operations to Bus 0 return the ECAM data for Device 0, Function 0.
Configuration write accesses across the PCI Express bus are non-posted writes and block the AXI4-Lite interface while they are in progress. Because of this, system software is not able to service an interrupt if one were to occur. However, interrupts due to abnormal terminations of configuration transactions can generate interrupts. ECAM read transactions block subsequent Requester read TLPs until the configuration read completions packet is returned to allow unique identification of the completion packet.
|1:0||Byte Address||Ignored for this implementation. The s_axi_ctl_wstrb[3:0] signals define byte enables for ECAM accesses.|
|7:2||Register Number||Register within the configuration space to access.|
|11:8||Extended Register Number||Along with Register Number, allows access to PCI Express Extended Configuration Space.|
|14:12||Function Number||Function Number to completer.|
|19:15||Device Number||Device Number to completer.|
|27:20||Bus Number||Bus Number to completer.|