The interface signals for the Bridge are described in the following table.
| Signal Name | I/O | Description |
|---|---|---|
| axi_aresetn | O |
In Endpoint configuration, reset signal for the S_AXIB and M_AXIB interfaces. axi_aresetn deasserts after a function has transitioned into D0_active power state (configured and enabled). In Root Port configuration, axi_aresetn deasserts after GT transceivers are initialized (assertion of Phy Ready, independent from PCIe link status). |
| axi_ctl_aresetn | O |
Reset signal for the S_AXIL interface. In Endpoint configuration, axi_ctl_aresetn deasserts after a function has transitioned into D0_active power state (configured and enabled). In Root Port configuration, axi_ctl_aresetn deasserts after GT transceivers are initialized (assertion of Phy Ready, independent from PCIe link status). |
| axi_aclk | O |
PCIe derived clock output for M_AXIB, S_AXIB, and S_AXIL interfaces. axi_aclk is a derived clock from the TXOUTCLK pin from the GT block; it is not expected to run continuously while axi_aresetn is asserted. |
| interrupt_out | O | Interrupt signal. It is asserted for as long as there exists at least one bit asserted in the Interrupt Decode register and is not masked in the Interrupt Mask register, and/or asserted in the Interrupt Decode 2 register and is not masked in the Interrupt Decode 2 Mask register. |
| interrupt_out_msi_vec0to31 | O | Interrupt signal. It is asserted for as long as
there exists at least one bit asserted in the MSI Decode 31-0
register and is not masked in the Interrupt Mask 1 register. Only available in Root Port configuration with Interrupt Decode mode. |
| interrupt_out_msi_vec32to63 | O | Interrupt signal. It is asserted for as long as
there exists at least one bit asserted in the MSI Decode 63-32
register and is not masked in the Interrupt Mask 2 register. Only available in Root Port configuration with Interrupt Decode mode. |
| soft_reset_n | I |
This pin is intended to be user driven reset when
link down, Function Level Reset, Dynamic Function eXchange, or
another error condition defined by user has occurred. It is not
required to be toggled during initial link up operation. When used, all PCIe traffic must be in quiesce state. The signal must be asserted for longer than the Completion Timeout value (typically 50 ms). 0: Resets all internal Bridge engines and registers as well as asserts axi_aresetn and axi_ctl_aresetn signals while maintaining PCIe link up. 1: Normal operation. |
| sys_rst_n | I | Reset from the PCIe edge connector reset signal. |
| phy_rdy_out_sd | I | Active-High signal that indicates when Phy is ready. This signal is from the Phy block. |
| user_lnk_up_sd | I | Active-High identifies that the PCI Express core is linked up with a host device. This signal is from the PCIe block |
| user_clk_sd | I | User clock from the PCIe block. All of the QDMA blocks use this clock |
| user_reset_sd | I | Active-High user reset signals from PCIe block. |