Status bits out of each engine can be used for initial debug of the subsystem. Per channel interface provides important status to the user application.
|Channel control register run bit.
|Asserted when the channel has interrupt pending.
|On an AXIST interface this bit indicates the last data indicated by the EOP bit has been posted.
|A descriptor has finished transferring data from the source and posted it to the destination.
|Descriptor_Done and Stop bit set in the descriptor.
|Descriptor_Done and Completed bit set in the descriptor.
|Channel descriptor buffer is not empty or DMA requests are outstanding.