clock output for m_axi* and s_axi* interfaces. axi_aclk is a derived clock from the
TXOUTCLK pin from the GT block; it is not expected to run continuously while
axi_aresetn is asserted.
||AXI reset signal synchronous with the clock provided on the
axi_aclk output. This reset should drive all corresponding AXI Interconnect aresetn
||Active-High Identifies that the PCI Express core is linked up with a host device. This
signal is from the integrated block for PCIe.
||Active-High signal that indicates when Phy is ready. This
signal is from the Phy block.
||User clock from the PCIe block. All of the QDMA blocks use this
||Active-High user reset signals from the PCIe block.