- Supports one AXI slave interface for accessing configuration and status registers.
- Supports one AXI master interface for code fetch.
- Supports two AXI master interface for model parameters loading.
- Supports 1-5 AXI master interface for accessing input/output/intermediate feature map stored in the HBM.
- Supports all AXI master interfaces with 256-bit width.
- DPU functionality includes the following:
- Configurable number of processing engines (PE).
- Convolution and deconvolution
- Max pooling
- Average pooling
- ReLU, ReLU6, and Leaky ReLU
- Concat
- Elementwise-sum
- Dilation
- Reorg
- Fully connected layer
- Batch normalization
- Split