Interface Ports - 1.0 English

Table 1. Lossless Compression IP Ports
Port Name	I/O	Clock	Description
s_aclk	I	s_aclk	Clock signal for the core.
s_aresetn	I	s_aclk	Active-Low reset signal for the core.
s_axis_tdata[dw-1:0]	I	s_aclk	Input AXI4-Stream data. dw is Input Data Width
s_axis_tkeep[dw/8-1:0]	I	s_aclk	Input AXI4-Stream signal. Indicates the bytes in the data that are valid. dw is Input Data Width
s_axis_tvalid	I	s_aclk	Input AXI4-Stream data valid signal.
s_axis_tlast	I	s_aclk	Input AXI4-Stream signal. Indicates the last beat of the current packet.
s_axis_tready	O	s_aclk	Output AXI4-Stream signal. Indicates that the core is ready to consume another beat of data.
m_axis_tdata[255:0]	O	s_aclk	Output AXI4-Stream data.
m_axis_tkeep[31:0]	O	s_aclk	Output AXI4-Stream signal. Indicates the bytes in the data that are valid.
m_axis_tvalid	O	s_aclk	Output AXI4-Stream data valid signal.
m_axis_tlast	O	s_aclk	Output AXI4-Stream signal. Indicates the last beat of the current packet.
m_axis_tready	I	s_aclk	Input AXI4-Stream signal. Indicates that the core is ready to consume another beat of data.
err_info[2:0]	O	s_aclk	This is a 3-bit port indicating errors in the file header part of the compressed file passed to the IP. Bit-0 : There can be errors in any part of the file header. Bit-1: This bit will go high whenever the starting part of the header has neither GZIP nor ZLIB format. Bit-2 : Reserved.