The Warp Initializer and Warp Filter cores have only one clock domain. All the interfaces, (the AXI4 interface), and the memory mapped AXI4 interface use the ap_clk pin as their clock source.
The Warp Initializer and Warp Filter cores have only one clock domain. All the interfaces, (the AXI4 interface), and the memory mapped AXI4 interface use the ap_clk pin as their clock source.