Port Descriptions - 1.0 English

DPUCVDX8H for Convolutional Neural Networks LogiCORE IP Product Guide (PG403)

Document ID
PG403
Release Date
2022-02-28
Version
1.0 English
Some of the DPU top-level interfaces are shown in the following figure. For a detailed description of I/O ports, see I/O Signals.
Figure 1. DPU IP Ports