An example design that demonstrates basic core functionality for the customized IP is available for AXI4-Stream Infrastructure IP cores. The example design is an independent Vivado® project populated with the customized IP along with additional IPs including example master(s), example slave(s), clocking and reset blocks. A synthesizable top-level HDL file is provided that instantiates and wires together the IPs shown in This Figure. If the parent Vivado project is configured for a Xilinx supported board, then the physical board constraints are also provided. A simulation-only demo test bench for the example design is also provided and discussed in further in the Test Bench.
IMPORTANT: The example design does not exhaustively demonstrate all the features of the IP. It is not a verification test bench.