The example design shows basic functionality by instantiating a synthesizable AXI4-Stream example master which sends transfers to an AXI4-Stream example slave. After a fixed number of transfers, the master completes and asserts the done output signal. The example slave receives the transfers and performs a null operation on the payload to emulate data processing. Once all transfers are received by the example slave the idle output signal is asserted. The example master and example slave generates a subset of AXI4-Stream protocol compliant transfers only. When the example master done output signal and the example slave idle output signal are both asserted then the done output pin is asserted. If this project is configured for a Xilinx® reference board then the done signal is tied to an LED output.
A Clocking Wizard core is present to interface with an external differential clock input and to provide a clock output suitable for the design to easily meet timing closure. If the project is configured for a Xilinx reference board, then the Clocking Wizard is configured to specify the differential clock input constraints for the board.
A LogiCore Processor System Reset block is present to interface with an external reset input and to provide a de-bounced active Low system reset. If the project is configured for a Xilinx reference board, then the Processor System Reset (Proc Sys Reset) core is configured to specify the reset input constraint for the board.