Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
•Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
•If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the LOCKED port.
•If your outputs go to 0, check your licensing.