When designing systems using AXI4-Stream Infrastructure IP Suite, the first step is to establish the topology of the system. This requires an understanding of the main interface characteristics of each AXI4-Stream master and slave that needs to be able to communicate together. AXI4-Stream masters and slaves then need to be grouped by desired connectivity into a system with one or more AXI4-Stream Infrastructure IP blocks tying them together so they can exchange data.
In general, try to establish the system partitioning/topology to use multiple smaller/simpler interconnects than a single large interconnect, especially in systems with a large number of devices. For example, combinations of N master x 1 slaves interconnects and 1 master x N slave interconnects are generally preferable to MxN interconnects in terms of area, latency, and throughput. MxN interconnect when required for performance or connectivity requirements should try to limit the number of endpoints or specify sparse connectivity to reduce resource utilization.
The Xilinx Vivado AXI Reference Guide (UG1037) [Ref 3] provides information about AXI4-Stream protocol usage guidelines and conventions; much of the AXI system optimizations information described for AXI Interconnect is applicable to AXI4-Stream Infrastructure IP Suite. The Xilinx AXI Reference Guide should be reviewed and consulted before designing or structuring systems around the AXI4-Stream Infrastructure IP.
After the number and topology of AXI4-Stream Infrastructure IP systems have been determined, the next step is to tailor each AXI4-Stream Infrastructure IP system to have the correct set of optional interface signals and set signals’ widths as needed. This sets up the interface signal set for the AXI4-Stream Infrastructure IP to ensure that data can be exchanged and routed as needed across the system.
Finally, the AXI4-Stream Infrastructure IP system should be optimized and fine-tuned to fit its application. This includes tuning FIFOs, width converters, clock converters, arbiters, and register slices (pipeline stages) as needed to balance area, timing, performance, and ease-of-use.