The AXI4-Stream Infrastructure IP Suite provides active-Low reset inputs for every clock input on the IP. Each reset input must be synchronized to the associated ACLK input of the interface. To ensure data is not lost during reset deassertion across multiple interfaces of the AXI4-Stream Infrastructure IP systems (operating in potentially different clock domains), the AXI4-Stream Infrastructure IP deasserts all TREADY and TVALID outputs until the clock cycle after their source logic has internally exited reset. Any endpoint IP driving TREADY or TVALID inputs to the AXI4-Stream Infrastructure IP should also deassert these signals until the clock cycle after they have exited reset internally.
These guidelines ensure that endpoint IPs can internally come out of reset at different times (due to internal reset pipelining) and no data will be exchanged until both are internally out of reset.
RECOMMENDED: Any endpoint should deassert TREADY and TVALID within 8 clock cycles of reset assertion. ARESETn should also be asserted for at least 16 cycles of the slowest system clock to ensure that all AXI4-Stream interfaces in the system enter reset and have time to deassert their TREADY/TVALID outputs before coming back out of reset.