A behavioral Verilog test bench that wraps around the example design top level is provided when the example design output product is generated. The test bench provides clocking and reset stimulus to the example design top level to run simulations on the example design. It monitors the done output to signal simulation completion. The test bench is useful for getting familiar with the signaling on the core by observing the simulation waveforms. The test bench can be used with all simulation outputs from behavioral RTL through post-implementation timing.
In the example design, the simulation sources file set includes the test bench. To run the test bench, select the Run Simulation option in the Vivado® Flow Navigator. When the simulation is open, enter the run all command to run the simulation to completion. Output similar to code shown below should be generated if the simulation completes successfully.
1937.60ns: exdes_tb: Starting testbench
2017.60ns: exdes_tb: Asserting reset for 16 cycles
2097.60ns: exdes_tb: Reset complete
68480.00ns: exdes_tb: SIMULATION PASSED
68480.00ns: exdes_tb: Test Completed Successfully