The following table shows the revision history for this document.
|
Section |
Revision Summary |
|---|---|
|
05/11/2022 Version 1.1 |
|
|
Updated Control Register |
|
|
11/10/2021 Version 1.1 |
|
|
General updates |
Updated for the 2021.2 release. |
|
08/06/2021 Version 1.1 |
|
|
General updates |
Added Versal example design support. |
|
02/04/2021 Version 1.1 |
|
|
General updates |
Updated for version 1.1. |
|
12/06/2019 Version 1.0 |
|
|
Software flow update |
Updated the Synthesizable Design Section with new Vitis flow for software. |
|
12/05/2018 Version 1.0 |
|
|
Updated the register addresses for Gamma look-up table 0, Gamma look-up table 1, and Gamma look-up table 2. |
|
|
10/04/2017 Version 1.0 |
|
|
General updates |
Initial Xilinx release. |