- User-selectable number of probe ports and probe width.
- User-selectable storage target such as block RAM and UltraRAM
- Multiple probe ports, which can be combined into a single trigger condition.
- User-selectable AXI slots to debug AXI interfaces in a design.
- Configurable options for AXI interfaces including interface types and trace sample depth.
- Data and trigger property for probes.
- Number of comparators and the width for each probe and individual ports within interfaces.
- Input/output cross-triggering interfaces.
- Configurable pipelining for input probes.
- AXI4-MM and AXI4-Stream protocol checking.
For more information about the ILA core, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).