ILA Ports - 1.1 English

Integrated Logic Analyzer (ILA) with AXI4-Stream Interface LogiCORE IP Product Guide (PG357)

Document ID
PG357
Release Date
2020-11-23
Version
1.1 English
Revision
Table 1. ILA Ports
Port Name I/O Description
clk I Design clock that clocks all trigger and storage logic.
probe<n>[<m> – 1:0] I

Probe port input. The probe port number <n> is in the range from 0 to 511. The probe port width (denoted by <m>) is in the range of 1 to 1024.

You must declare this port as a vector. For a 1-bit port, use probe<n>[0:0].

trig_out O The trig_out port can be generated either from the trigger condition or from an external trig_in port. There is a run time control from the Logic Analyzer to switch between trigger condition and trig_in to drive trig_out.
trig_in I Input trigger port used in process based system for Embedded Cross Trigger. Can be connected to another ILA to create cascading Trigger.
slot_<p>_<intf_name> I

Slot interface.

The type of the interface <intf_name> is created dynamically based on the slot_<p>_<intf_name> interface type parameter. The individual ports within the interfaces are available for monitoring in the hardware manager.

trig_out_ack I An acknowledgment to trig_out.
trig_in_ack O An acknowledgment to trig_in.
resetn I ILA Input Type when set to ‘Interface Monitor’, this port should be the same reset signal that is synchronous to the design logic that is attached to the Slot_<p>_<intf_name> ports of the ILA core.
S_AXIS I/O

Optional port.

Used for manual connection with AXI Debug Hub core when ‘Enable AXI4-Stream Interface for Manul Connection to AXI Debug Hub’ is selected in Advanced Options.

M_AXIS I/O

Optional port.

Used for manual connection with AXI Debug Hub core when ‘Enable AXI4-Stream Interface for Manual Connection to AXI Debug Hub’ is selected in ‘Advanced Options’.

aresetn I

Optional port.

Used for manual connection with AXI Debug Hub core when ‘Enable AXI4-Stream Interface for Manual Connection to AXI Debug Hub’ is selected in ‘Advanced Options’. This port should be synchronous with reset port of AXI Debug Hub.

aclk I

Optional port.

Used for manual connection with AXI Debug Hub core when ‘Enable AXI4-Stream Interface for Manual Connection to AXI Debug Hub’ is selected in ‘Advanced Options’. This port should be synchronous with clock port of AXI Debug Hub.