AXI4-Stream User Interface - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2022-07-21
Version
1.1 English

The user-side data interface is Segmented AXI4-Stream with per-segment channel control which represents a simple packet interface designed to allow easy integration of the ILKNF into a system. The width of the user-side AXI4-Stream interface is determined for each configuration based on the aggregate bandwidth, and can have the following values: 2048-, 1024-, 1536-, 768- and 512-bit. The AXI4-Stream bus is divided into 128-bit segments.

Note: In the tables, <M> is the segment number 0 to 15.
Table 1. TX Segmented AXI4-Stream Interface Signal Descriptions
Port Name Clock Domain I/O Description
tx_axis_tdata<M>[127:0] c0_axi_clk I Transmit segment<M> AXI4-Stream data. This bus receives input data from the user logic. The value of the bus is captured in every cycle for which tx_axis_tuser_ena<M> is sampled as 1.
tx_axis_tuser_ena<M> c0_axi_clk I Transmit segment<M> enable. This signal is used to enable the TX AXI4-Stream interface. All signals on the AXI4-Stream interface are sampled only in cycles during which tx_axis_tuser_ena<M> is sampled as 1.
tx_axis_tuser_sop<M> c0_axi_clk I Transmit segment<M> start of packet. This signal is used to indicate the SOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_axis_tuser_ena<M> is sampled as 1.
tx_axis_tuser_eop<M> c0_axi_clk I Transmit segment<M> end of packet. This signal is used to indicate the EOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_axis_tuser_ena<M> is sampled as 1.
tx_axis_tuser_err<M> c0_axi_clk I Transmit segment<M> error. This signal is used to indicate that a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_axis_tuser_ena<M> and tx_axis_tuser_eop<M> are sampled as 1.
tx_axis_tuser_mty<M>[3:0] c0_axi_clk I

Transmit segment<M> empty. This bus is used to indicate how many bytes of the tx_axis_tdata<M>[127:0] bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that tx_axis_tuser_ena<M> and tx_axis_tuser_eop<M> are sampled as 1.

When tx_axis_tuser_eop<M> and tx_axis_tuser_err<M> are sampled as 1, the value of tx_axis_tuser_mty<M>[2:0] is ignored and treated as if it was 000. tx_axis_tuser_mty<M>[3] is used as usual.
tx_axis_tuser_chan<M>[10:0] c0_axi_clk I

Transmit segment<M> channel number. This bus receives the channel number for the packet being written. The value of the bus is captured in every cycle for which tx_axis_tuser_ena<M> is sampled as 1.

In packet mode, the channel number remains the same for the duration of the packet transfer from Start of Packet (SOP) to End of Packet (EOP). In burst-interleaved mode, the channel number can change for each burst.
tx_axis_tuser_bctl<M> c0_axi_clk I

Transmit segment<M> force insertion of burst control word. This input is used to force the insertion of a burst control word. When tx_axis_tuser_bctl<M> and tx_axis_tuser_ena<M>, are sampled as 1, a Burst Control word is inserted before the data on the tx_axis_tdata<M> [127:0] bus is transmitted even if one is not required to observe the value of the c0_ctl_tx_burstmax field of the CFG_C0_TX_MAIN_REG register.

This input is used by the enhanced scheduling algorithm, external to the Interlaken IP Core.

Important: Enhanced scheduling is required for the segmented AXI4-Stream. If you do not control the enhanced scheduling, the ILKNF subsystem automatically performs enhanced scheduling in order to avoid burst violations on the Interlaken interface.
c0_tx_ovfout c0_axi_clk O TX FIFO overflow signal. If asserted, this signal indicates that the backpressure mechanism provided by the c0_tx_rdyout signal has been violated and requires a reset to clear. The user logic must be designed to prevent the overflow of TX FIFO.
c0_tx_rdyout c0_axi_clk O Transmit Ready. This signal indicates whether the ILKNF subsystem TX path is ready to accept data and provides backpressure to the user logic. A value of 1 means the user logic can pass data to the core. A value of 0 means the user logic must stop transferring data to the core within the number of clocks indicated by the c0_ctl_tx_rdyout_thresh[3:0] register field of the CFG_C0_TX_MISC_REG register.
Note: For the TX AXI4-Stream it is implied that TREADY is continuously asserted (logic 1) to the user logic. A backpressure signal c0_tx_rdyout is used to control the flow of data through the TX path of the ILKNF subsystem.
Table 2. RX Segmented AXI4-Stream Interface Signal Descriptions
Port Name Clock Domain I/O Description
rx_axis_tdata<M>[127:0] c0_axi_clk I Receive segment<M> AXI4-Stream data. The value of the bus is only valid in cycles during which rx_axis_tuser_ena<M> is sampled as 1.
rx_axis_tuser_ena<M> c0_axi_clk I Receive segment<M> enable. This signal qualifies the other signals of the RX AXI4-Stream interface. The signals of the RX AXI4-Stream interface are only valid in cycles during which rx_axis_tuser_ena<M> is sampled as 1.
rx_axis_tuser_sop<M> c0_axi_clk I Receive segment<M> start of packet. This signal indicates the SOP when it is sampled as 1 and is only valid in cycles during which rx_axis_tuser_ena<M> is sampled as a 1.
rx_axis_tuser_eop<M> c0_axi_clk I Receive segment<M> end of packet. This signal indicates the EOP when it is sampled as 1 and is only valid in cycles during which rx_axis_tuser_ena<M> is sampled as a 1.
rx_axis_tuser_err<M> c0_axi_clk I Receive segment<M> error. This signal indicates that the current packet being received has an error when it is sampled as 1. This signal is only valid in cycles when both rx_axis_tuser_ena<M> and rx_axis_tuser_eop<M> are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet being received.
rx_axis_tuser_mty<M>[3:0] c0_axi_clk I

Receive segment<M> empty. This bus indicates how many bytes of the rx_axis_tdata<M>[127:0] bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both rx_axis_tuser_ena<M> and rx_axis_tuser_eop<M> are sampled as 1.

When rx_axis_tuser_err<M> and rx_axis_tuser_ena<M> are sampled as 1, the value of rx_axis_tuser_mty<M>[2:0] is always 000. rx_axis_tuser_mty<M>[3] is used as usual.
rx_axis_tuser_chan<M>[10:0] c0_axi_clk I Receive segment<M> channel number. The bus indicates the channel number of the in-flight packet and is only valid in cycles during which rx_axis_tuser_ena<M> is sampled as 1.
Note: For the RX AXI4-Stream it is implied that TREADY is continuously asserted (logic 1) from the user logic. There is no mechanism to control the flow of data through the RX path of the ILKNF subsystem.