Clocks - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2022-07-21
Version
1.1 English

The following table lists the clocks that are present in the ILKNF subsystem.

Table 1. Clocks
Clock Port Description
AXI4-Lite s_axi_clk AXI4-Lite processor interface clock
AXI c0_axi_clk AXI-S user interface clock.
core c0_core_clk Core clock.
serdes tx_serdes_clk[5:0] High-speed clocks for the GT interface.
serdes tx_alt_serdes_clk[5:0] Alternate low-frequency clocks for the GT interface.
serdes rx_serdes_clk[5:0] High-speed clocks for the GT interface.
serdes rx_alt_serdes_clk[5:0] Alternate low-frequency clocks for the GT interface.