System Clocks - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2022-07-21
Version
1.1 English

The apb3_clk signal is a mandatory clock which must be present and stable in all modes of operation. It is used for internal configuration and synchronization functions in addition to its use as a clock for the processor interface.